accel/tcg/cpu-ops.h

2  * TCG CPU-specific operations
7  * See the COPYING file in the top-level directory.
17 #include "exec/mmu-access-type.h"
19 #include "accel/tcg/tb-cpu-state.h"
20 #include "tcg/tcg-mo.h"
24      * mttcg_supported: multi-threaded TCG is supported
27      *   - atomic instructions
28      *   - memory ordering primitives (barriers)
60      * the target-specific DisasContext, and then invoke translator_loop.
76      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
87      * state which are tracked insn-by-insn in the target-specific
100     /** @mmu_index: Callback for choosing softmmu mmu index */
130      * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
154      * If it is simpler to re-use the sysemu do_unaligned_access code,
191      * @tlb_fill_align: Handle a softmmu tlb miss
210      * for non-memory-access operations such as probing.
216      * @tlb_fill: Handle a softmmu tlb miss
249      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
255      * watchpoint whose address has matched should really fire, used by ARM
256      * and RISC-V
271      * target architecture requires re-execution of the branch, then