Lines Matching +full:dc +full:- +full:valid
4 * Copyright (C) 2016-2017 IBM Corp.
7 * COPYING file in the top-level directory.
17 #include "hw/qdev-properties.h"
64 mode = extract32(s->regs[WDT_CTRL], 5, 2); in aspeed_wdt_is_soc_reset_mode()
70 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; in aspeed_wdt_is_enabled()
83 return s->regs[WDT_STATUS]; in aspeed_wdt_read()
85 return s->regs[WDT_RELOAD_VALUE]; in aspeed_wdt_read()
88 "%s: read from write-only reg at offset 0x%" in aspeed_wdt_read()
92 return s->regs[WDT_CTRL]; in aspeed_wdt_read()
94 return s->regs[WDT_RESET_WIDTH]; in aspeed_wdt_read()
96 return s->regs[WDT_RESET_MASK1]; in aspeed_wdt_read()
109 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", in aspeed_wdt_read()
120 if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { in aspeed_wdt_reload()
121 reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, in aspeed_wdt_reload()
122 s->pclk_freq); in aspeed_wdt_reload()
124 reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; in aspeed_wdt_reload()
128 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); in aspeed_wdt_reload()
134 uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; in aspeed_wdt_reload_1mhz()
137 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); in aspeed_wdt_reload_1mhz()
170 "%s: write to read-only reg at offset 0x%" in aspeed_wdt_write()
174 s->regs[WDT_RELOAD_VALUE] = data; in aspeed_wdt_write()
178 s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; in aspeed_wdt_write()
179 awc->wdt_reload(s); in aspeed_wdt_write()
183 data = awc->sanitize_ctrl(data); in aspeed_wdt_write()
186 s->regs[WDT_CTRL] = data; in aspeed_wdt_write()
187 awc->wdt_reload(s); in aspeed_wdt_write()
189 s->regs[WDT_CTRL] = data; in aspeed_wdt_write()
190 timer_del(s->timer); in aspeed_wdt_write()
192 s->regs[WDT_CTRL] = data; in aspeed_wdt_write()
196 if (awc->reset_pulse) { in aspeed_wdt_write()
197 awc->reset_pulse(s, data & WDT_POLARITY_MASK); in aspeed_wdt_write()
199 s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; in aspeed_wdt_write()
200 s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; in aspeed_wdt_write()
205 s->regs[WDT_RESET_MASK1] = data; in aspeed_wdt_write()
225 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", in aspeed_wdt_write()
245 .valid.min_access_size = 1,
246 .valid.max_access_size = 4,
247 .valid.unaligned = false,
255 s->regs[WDT_STATUS] = awc->default_status; in aspeed_wdt_reset()
256 s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value; in aspeed_wdt_reset()
257 s->regs[WDT_RESTART] = 0; in aspeed_wdt_reset()
258 s->regs[WDT_CTRL] = awc->sanitize_ctrl(0); in aspeed_wdt_reset()
259 s->regs[WDT_RESET_WIDTH] = 0xFF; in aspeed_wdt_reset()
261 timer_del(s->timer); in aspeed_wdt_reset()
267 uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; in aspeed_wdt_timer_expired()
270 if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { in aspeed_wdt_timer_expired()
271 timer_del(s->timer); in aspeed_wdt_timer_expired()
272 s->regs[WDT_CTRL] = 0; in aspeed_wdt_timer_expired()
277 s->iomem.addr); in aspeed_wdt_timer_expired()
279 timer_del(s->timer); in aspeed_wdt_timer_expired()
290 assert(s->scu); in aspeed_wdt_realize()
292 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); in aspeed_wdt_realize()
298 s->pclk_freq = PCLK_HZ; in aspeed_wdt_realize()
300 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, in aspeed_wdt_realize()
301 TYPE_ASPEED_WDT, awc->iosize); in aspeed_wdt_realize()
302 sysbus_init_mmio(sbd, &s->iomem); in aspeed_wdt_realize()
312 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_wdt_class_init() local
314 dc->desc = "ASPEED Watchdog Controller"; in aspeed_wdt_class_init()
315 dc->realize = aspeed_wdt_realize; in aspeed_wdt_class_init()
316 device_class_set_legacy_reset(dc, aspeed_wdt_reset); in aspeed_wdt_class_init()
317 set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); in aspeed_wdt_class_init()
318 dc->vmsd = &vmstate_aspeed_wdt; in aspeed_wdt_class_init()
319 device_class_set_props(dc, aspeed_wdt_properties); in aspeed_wdt_class_init()
320 dc->desc = "Aspeed watchdog device"; in aspeed_wdt_class_init()
334 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_2400_wdt_class_init() local
337 dc->desc = "ASPEED 2400 Watchdog Controller"; in aspeed_2400_wdt_class_init()
338 awc->iosize = 0x20; in aspeed_2400_wdt_class_init()
339 awc->ext_pulse_width_mask = 0xff; in aspeed_2400_wdt_class_init()
340 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; in aspeed_2400_wdt_class_init()
341 awc->wdt_reload = aspeed_wdt_reload; in aspeed_2400_wdt_class_init()
342 awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl; in aspeed_2400_wdt_class_init()
343 awc->default_status = 0x03EF1480; in aspeed_2400_wdt_class_init()
344 awc->default_reload_value = 0x03EF1480; in aspeed_2400_wdt_class_init()
358 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; in aspeed_2500_wdt_reset_pulse()
360 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; in aspeed_2500_wdt_reset_pulse()
362 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; in aspeed_2500_wdt_reset_pulse()
364 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; in aspeed_2500_wdt_reset_pulse()
371 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_2500_wdt_class_init() local
374 dc->desc = "ASPEED 2500 Watchdog Controller"; in aspeed_2500_wdt_class_init()
375 awc->iosize = 0x20; in aspeed_2500_wdt_class_init()
376 awc->ext_pulse_width_mask = 0xfffff; in aspeed_2500_wdt_class_init()
377 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; in aspeed_2500_wdt_class_init()
378 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; in aspeed_2500_wdt_class_init()
379 awc->wdt_reload = aspeed_wdt_reload_1mhz; in aspeed_2500_wdt_class_init()
380 awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl; in aspeed_2500_wdt_class_init()
381 awc->default_status = 0x014FB180; in aspeed_2500_wdt_class_init()
382 awc->default_reload_value = 0x014FB180; in aspeed_2500_wdt_class_init()
394 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_2600_wdt_class_init() local
397 dc->desc = "ASPEED 2600 Watchdog Controller"; in aspeed_2600_wdt_class_init()
398 awc->iosize = 0x40; in aspeed_2600_wdt_class_init()
399 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ in aspeed_2600_wdt_class_init()
400 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; in aspeed_2600_wdt_class_init()
401 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; in aspeed_2600_wdt_class_init()
402 awc->wdt_reload = aspeed_wdt_reload_1mhz; in aspeed_2600_wdt_class_init()
403 awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; in aspeed_2600_wdt_class_init()
404 awc->default_status = 0x014FB180; in aspeed_2600_wdt_class_init()
405 awc->default_reload_value = 0x014FB180; in aspeed_2600_wdt_class_init()
417 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_1030_wdt_class_init() local
420 dc->desc = "ASPEED 1030 Watchdog Controller"; in aspeed_1030_wdt_class_init()
421 awc->iosize = 0x80; in aspeed_1030_wdt_class_init()
422 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ in aspeed_1030_wdt_class_init()
423 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; in aspeed_1030_wdt_class_init()
424 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; in aspeed_1030_wdt_class_init()
425 awc->wdt_reload = aspeed_wdt_reload_1mhz; in aspeed_1030_wdt_class_init()
426 awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; in aspeed_1030_wdt_class_init()
427 awc->default_status = 0x014FB180; in aspeed_1030_wdt_class_init()
428 awc->default_reload_value = 0x014FB180; in aspeed_1030_wdt_class_init()
440 DeviceClass *dc = DEVICE_CLASS(klass); in aspeed_2700_wdt_class_init() local
443 dc->desc = "ASPEED 2700 Watchdog Controller"; in aspeed_2700_wdt_class_init()
444 awc->iosize = 0x80; in aspeed_2700_wdt_class_init()
445 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ in aspeed_2700_wdt_class_init()
446 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; in aspeed_2700_wdt_class_init()
447 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; in aspeed_2700_wdt_class_init()
448 awc->wdt_reload = aspeed_wdt_reload_1mhz; in aspeed_2700_wdt_class_init()
449 awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; in aspeed_2700_wdt_class_init()
450 awc->default_status = 0x014FB180; in aspeed_2700_wdt_class_init()
451 awc->default_reload_value = 0x014FB180; in aspeed_2700_wdt_class_init()