Lines Matching +full:ati +full:- +full:target
4 * Copyright Red Hat, Inc. 2012-2015
10 * the COPYING file in the top-level directory.
18 #include "qemu/error-report.h"
19 #include "qemu/main-loop.h"
26 #include "hw/qdev-properties.h"
56 trace_vfio_quirk_rom_in_denylist(vdev->vbasedev.name, in vfio_opt_rom_in_denylist()
108 VFIOPCIDevice *vdev = window->vdev; in vfio_generic_window_quirk_address_read()
110 return vfio_region_read(&vdev->bars[window->bar].region, in vfio_generic_window_quirk_address_read()
111 addr + window->address_offset, size); in vfio_generic_window_quirk_address_read()
119 VFIOPCIDevice *vdev = window->vdev; in vfio_generic_window_quirk_address_write()
122 window->window_enabled = false; in vfio_generic_window_quirk_address_write()
124 vfio_region_write(&vdev->bars[window->bar].region, in vfio_generic_window_quirk_address_write()
125 addr + window->address_offset, data, size); in vfio_generic_window_quirk_address_write()
127 for (i = 0; i < window->nr_matches; i++) { in vfio_generic_window_quirk_address_write()
128 if ((data & ~window->matches[i].mask) == window->matches[i].match) { in vfio_generic_window_quirk_address_write()
129 window->window_enabled = true; in vfio_generic_window_quirk_address_write()
130 window->address_val = data & window->matches[i].mask; in vfio_generic_window_quirk_address_write()
131 trace_vfio_quirk_generic_window_address_write(vdev->vbasedev.name, in vfio_generic_window_quirk_address_write()
132 memory_region_name(window->addr_mem), data); in vfio_generic_window_quirk_address_write()
148 VFIOPCIDevice *vdev = window->vdev; in vfio_generic_window_quirk_data_read()
152 data = vfio_region_read(&vdev->bars[window->bar].region, in vfio_generic_window_quirk_data_read()
153 addr + window->data_offset, size); in vfio_generic_window_quirk_data_read()
155 if (window->window_enabled) { in vfio_generic_window_quirk_data_read()
156 data = vfio_pci_read_config(&vdev->pdev, window->address_val, size); in vfio_generic_window_quirk_data_read()
157 trace_vfio_quirk_generic_window_data_read(vdev->vbasedev.name, in vfio_generic_window_quirk_data_read()
158 memory_region_name(window->data_mem), data); in vfio_generic_window_quirk_data_read()
168 VFIOPCIDevice *vdev = window->vdev; in vfio_generic_window_quirk_data_write()
170 if (window->window_enabled) { in vfio_generic_window_quirk_data_write()
171 vfio_pci_write_config(&vdev->pdev, window->address_val, data, size); in vfio_generic_window_quirk_data_write()
172 trace_vfio_quirk_generic_window_data_write(vdev->vbasedev.name, in vfio_generic_window_quirk_data_write()
173 memory_region_name(window->data_mem), data); in vfio_generic_window_quirk_data_write()
177 vfio_region_write(&vdev->bars[window->bar].region, in vfio_generic_window_quirk_data_write()
178 addr + window->data_offset, data, size); in vfio_generic_window_quirk_data_write()
205 VFIOPCIDevice *vdev = mirror->vdev; in vfio_generic_quirk_mirror_read()
209 (void)vfio_region_read(&vdev->bars[mirror->bar].region, in vfio_generic_quirk_mirror_read()
210 addr + mirror->offset, size); in vfio_generic_quirk_mirror_read()
212 data = vfio_pci_read_config(&vdev->pdev, addr, size); in vfio_generic_quirk_mirror_read()
213 trace_vfio_quirk_generic_mirror_read(vdev->vbasedev.name, in vfio_generic_quirk_mirror_read()
214 memory_region_name(mirror->mem), in vfio_generic_quirk_mirror_read()
223 VFIOPCIDevice *vdev = mirror->vdev; in vfio_generic_quirk_mirror_write()
225 vfio_pci_write_config(&vdev->pdev, addr, data, size); in vfio_generic_quirk_mirror_write()
226 trace_vfio_quirk_generic_mirror_write(vdev->vbasedev.name, in vfio_generic_quirk_mirror_write()
227 memory_region_name(mirror->mem), in vfio_generic_quirk_mirror_write()
259 uint64_t data = vfio_pci_read_config(&vdev->pdev, in vfio_ati_3c3_quirk_read()
262 trace_vfio_quirk_ati_3c3_read(vdev->vbasedev.name, data); in vfio_ati_3c3_quirk_read()
282 QLIST_INIT(&quirk->ioeventfds); in vfio_quirk_alloc()
283 quirk->mem = g_new0(MemoryRegion, nr_mem); in vfio_quirk_alloc()
284 quirk->nr_mem = nr_mem; in vfio_quirk_alloc()
292 memory_region_del_eventfd(ioeventfd->mr, ioeventfd->addr, ioeventfd->size, in vfio_ioeventfd_exit()
293 true, ioeventfd->data, &ioeventfd->e); in vfio_ioeventfd_exit()
295 if (ioeventfd->vfio) { in vfio_ioeventfd_exit()
299 vfio_ioeventfd.flags = ioeventfd->size; in vfio_ioeventfd_exit()
300 vfio_ioeventfd.data = ioeventfd->data; in vfio_ioeventfd_exit()
301 vfio_ioeventfd.offset = ioeventfd->region->fd_offset + in vfio_ioeventfd_exit()
302 ioeventfd->region_addr; in vfio_ioeventfd_exit()
303 vfio_ioeventfd.fd = -1; in vfio_ioeventfd_exit()
305 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_IOEVENTFD, &vfio_ioeventfd)) { in vfio_ioeventfd_exit()
308 memory_region_name(ioeventfd->mr), ioeventfd->addr, in vfio_ioeventfd_exit()
309 ioeventfd->size, ioeventfd->data); in vfio_ioeventfd_exit()
312 qemu_set_fd_handler(event_notifier_get_fd(&ioeventfd->e), in vfio_ioeventfd_exit()
316 event_notifier_cleanup(&ioeventfd->e); in vfio_ioeventfd_exit()
317 trace_vfio_ioeventfd_exit(memory_region_name(ioeventfd->mr), in vfio_ioeventfd_exit()
318 (uint64_t)ioeventfd->addr, ioeventfd->size, in vfio_ioeventfd_exit()
319 ioeventfd->data); in vfio_ioeventfd_exit()
327 QLIST_FOREACH_SAFE(ioeventfd, &quirk->ioeventfds, next, tmp) { in vfio_drop_dynamic_eventfds()
328 if (ioeventfd->dynamic) { in vfio_drop_dynamic_eventfds()
338 if (event_notifier_test_and_clear(&ioeventfd->e)) { in vfio_ioeventfd_handler()
339 vfio_region_write(ioeventfd->region, ioeventfd->region_addr, in vfio_ioeventfd_handler()
340 ioeventfd->data, ioeventfd->size); in vfio_ioeventfd_handler()
341 trace_vfio_ioeventfd_handler(memory_region_name(ioeventfd->mr), in vfio_ioeventfd_handler()
342 (uint64_t)ioeventfd->addr, ioeventfd->size, in vfio_ioeventfd_handler()
343 ioeventfd->data); in vfio_ioeventfd_handler()
355 if (vdev->no_kvm_ioeventfd) { in vfio_ioeventfd_init()
361 if (event_notifier_init(&ioeventfd->e, 0)) { in vfio_ioeventfd_init()
370 ioeventfd->mr = mr; in vfio_ioeventfd_init()
371 ioeventfd->addr = addr; in vfio_ioeventfd_init()
372 ioeventfd->size = size; in vfio_ioeventfd_init()
373 ioeventfd->data = data; in vfio_ioeventfd_init()
374 ioeventfd->dynamic = dynamic; in vfio_ioeventfd_init()
379 ioeventfd->region = region; in vfio_ioeventfd_init()
380 ioeventfd->region_addr = region_addr; in vfio_ioeventfd_init()
382 if (!vdev->no_vfio_ioeventfd) { in vfio_ioeventfd_init()
386 vfio_ioeventfd.flags = ioeventfd->size; in vfio_ioeventfd_init()
387 vfio_ioeventfd.data = ioeventfd->data; in vfio_ioeventfd_init()
388 vfio_ioeventfd.offset = ioeventfd->region->fd_offset + in vfio_ioeventfd_init()
389 ioeventfd->region_addr; in vfio_ioeventfd_init()
390 vfio_ioeventfd.fd = event_notifier_get_fd(&ioeventfd->e); in vfio_ioeventfd_init()
392 ioeventfd->vfio = !ioctl(vdev->vbasedev.fd, in vfio_ioeventfd_init()
396 if (!ioeventfd->vfio) { in vfio_ioeventfd_init()
397 qemu_set_fd_handler(event_notifier_get_fd(&ioeventfd->e), in vfio_ioeventfd_init()
401 memory_region_add_eventfd(ioeventfd->mr, ioeventfd->addr, ioeventfd->size, in vfio_ioeventfd_init()
402 true, ioeventfd->data, &ioeventfd->e); in vfio_ioeventfd_init()
404 size, data, ioeventfd->vfio); in vfio_ioeventfd_init()
418 !vdev->bars[4].ioport || vdev->bars[4].region.size < 256) { in vfio_vga_probe_ati_3c3_quirk()
424 memory_region_init_io(quirk->mem, OBJECT(vdev), &vfio_ati_3c3_quirk, vdev, in vfio_vga_probe_ati_3c3_quirk()
425 "vfio-ati-3c3-quirk", 1); in vfio_vga_probe_ati_3c3_quirk()
426 memory_region_add_subregion(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, in vfio_vga_probe_ati_3c3_quirk()
427 3 /* offset 3 bytes from 0x3c0 */, quirk->mem); in vfio_vga_probe_ati_3c3_quirk()
429 QLIST_INSERT_HEAD(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks, in vfio_vga_probe_ati_3c3_quirk()
432 trace_vfio_quirk_ati_3c3_probe(vdev->vbasedev.name); in vfio_vga_probe_ati_3c3_quirk()
436 * Newer ATI/AMD devices, including HD5450 and HD7850, have a mirror to PCI
440 * data register. When the address is programmed to a range of 0x4000-0x4fff
442 * that read-only may be provided by hardware.
451 !vdev->vga || nr != 4) { in vfio_probe_ati_bar4_quirk()
456 window = quirk->data = g_malloc0(sizeof(*window) + in vfio_probe_ati_bar4_quirk()
458 window->vdev = vdev; in vfio_probe_ati_bar4_quirk()
459 window->address_offset = 0; in vfio_probe_ati_bar4_quirk()
460 window->data_offset = 4; in vfio_probe_ati_bar4_quirk()
461 window->nr_matches = 1; in vfio_probe_ati_bar4_quirk()
462 window->matches[0].match = 0x4000; in vfio_probe_ati_bar4_quirk()
463 window->matches[0].mask = vdev->config_size - 1; in vfio_probe_ati_bar4_quirk()
464 window->bar = nr; in vfio_probe_ati_bar4_quirk()
465 window->addr_mem = &quirk->mem[0]; in vfio_probe_ati_bar4_quirk()
466 window->data_mem = &quirk->mem[1]; in vfio_probe_ati_bar4_quirk()
468 memory_region_init_io(window->addr_mem, OBJECT(vdev), in vfio_probe_ati_bar4_quirk()
470 "vfio-ati-bar4-window-address-quirk", 4); in vfio_probe_ati_bar4_quirk()
471 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_ati_bar4_quirk()
472 window->address_offset, in vfio_probe_ati_bar4_quirk()
473 window->addr_mem, 1); in vfio_probe_ati_bar4_quirk()
475 memory_region_init_io(window->data_mem, OBJECT(vdev), in vfio_probe_ati_bar4_quirk()
477 "vfio-ati-bar4-window-data-quirk", 4); in vfio_probe_ati_bar4_quirk()
478 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_ati_bar4_quirk()
479 window->data_offset, in vfio_probe_ati_bar4_quirk()
480 window->data_mem, 1); in vfio_probe_ati_bar4_quirk()
482 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_ati_bar4_quirk()
484 trace_vfio_quirk_ati_bar4_probe(vdev->vbasedev.name); in vfio_probe_ati_bar4_quirk()
497 !vdev->vga || nr != 2 || !vdev->bars[2].mem64) { in vfio_probe_ati_bar2_quirk()
502 mirror = quirk->data = g_malloc0(sizeof(*mirror)); in vfio_probe_ati_bar2_quirk()
503 mirror->mem = quirk->mem; in vfio_probe_ati_bar2_quirk()
504 mirror->vdev = vdev; in vfio_probe_ati_bar2_quirk()
505 mirror->offset = 0x4000; in vfio_probe_ati_bar2_quirk()
506 mirror->bar = nr; in vfio_probe_ati_bar2_quirk()
508 memory_region_init_io(mirror->mem, OBJECT(vdev), in vfio_probe_ati_bar2_quirk()
510 "vfio-ati-bar2-4000-quirk", PCI_CONFIG_SPACE_SIZE); in vfio_probe_ati_bar2_quirk()
511 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_ati_bar2_quirk()
512 mirror->offset, mirror->mem, 1); in vfio_probe_ati_bar2_quirk()
514 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_ati_bar2_quirk()
516 trace_vfio_quirk_ati_bar2_probe(vdev->vbasedev.name); in vfio_probe_ati_bar2_quirk()
520 * Older ATI/AMD cards like the X550 have a similar window to that above.
535 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
555 VFIOPCIDevice *vdev = quirk->vdev; in vfio_nvidia_3d4_quirk_read()
557 quirk->state = NONE; in vfio_nvidia_3d4_quirk_read()
559 return vfio_vga_read(&vdev->vga->region[QEMU_PCI_VGA_IO_HI], in vfio_nvidia_3d4_quirk_read()
567 VFIOPCIDevice *vdev = quirk->vdev; in vfio_nvidia_3d4_quirk_write()
568 VFIONvidia3d0State old_state = quirk->state; in vfio_nvidia_3d4_quirk_write()
570 quirk->state = NONE; in vfio_nvidia_3d4_quirk_write()
575 quirk->state = SELECT; in vfio_nvidia_3d4_quirk_write()
576 trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name, in vfio_nvidia_3d4_quirk_write()
577 nv3d0_states[quirk->state]); in vfio_nvidia_3d4_quirk_write()
582 quirk->state = READ; in vfio_nvidia_3d4_quirk_write()
583 trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name, in vfio_nvidia_3d4_quirk_write()
584 nv3d0_states[quirk->state]); in vfio_nvidia_3d4_quirk_write()
589 quirk->state = WRITE; in vfio_nvidia_3d4_quirk_write()
590 trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name, in vfio_nvidia_3d4_quirk_write()
591 nv3d0_states[quirk->state]); in vfio_nvidia_3d4_quirk_write()
596 vfio_vga_write(&vdev->vga->region[QEMU_PCI_VGA_IO_HI], in vfio_nvidia_3d4_quirk_write()
610 VFIOPCIDevice *vdev = quirk->vdev; in vfio_nvidia_3d0_quirk_read()
611 VFIONvidia3d0State old_state = quirk->state; in vfio_nvidia_3d0_quirk_read()
612 uint64_t data = vfio_vga_read(&vdev->vga->region[QEMU_PCI_VGA_IO_HI], in vfio_nvidia_3d0_quirk_read()
615 quirk->state = NONE; in vfio_nvidia_3d0_quirk_read()
618 (quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) { in vfio_nvidia_3d0_quirk_read()
619 uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1); in vfio_nvidia_3d0_quirk_read()
621 data = vfio_pci_read_config(&vdev->pdev, offset, size); in vfio_nvidia_3d0_quirk_read()
622 trace_vfio_quirk_nvidia_3d0_read(vdev->vbasedev.name, in vfio_nvidia_3d0_quirk_read()
633 VFIOPCIDevice *vdev = quirk->vdev; in vfio_nvidia_3d0_quirk_write()
634 VFIONvidia3d0State old_state = quirk->state; in vfio_nvidia_3d0_quirk_write()
636 quirk->state = NONE; in vfio_nvidia_3d0_quirk_write()
639 quirk->offset = (uint32_t)data; in vfio_nvidia_3d0_quirk_write()
640 quirk->state = WINDOW; in vfio_nvidia_3d0_quirk_write()
641 trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name, in vfio_nvidia_3d0_quirk_write()
642 nv3d0_states[quirk->state]); in vfio_nvidia_3d0_quirk_write()
644 if ((quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) { in vfio_nvidia_3d0_quirk_write()
645 uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1); in vfio_nvidia_3d0_quirk_write()
647 vfio_pci_write_config(&vdev->pdev, offset, data, size); in vfio_nvidia_3d0_quirk_write()
648 trace_vfio_quirk_nvidia_3d0_write(vdev->vbasedev.name, in vfio_nvidia_3d0_quirk_write()
654 vfio_vga_write(&vdev->vga->region[QEMU_PCI_VGA_IO_HI], in vfio_nvidia_3d0_quirk_write()
669 if (vdev->no_geforce_quirks || in vfio_vga_probe_nvidia_3d0_quirk()
671 !vdev->bars[1].region.size) { in vfio_vga_probe_nvidia_3d0_quirk()
676 quirk->data = data = g_malloc0(sizeof(*data)); in vfio_vga_probe_nvidia_3d0_quirk()
677 data->vdev = vdev; in vfio_vga_probe_nvidia_3d0_quirk()
679 memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_nvidia_3d4_quirk, in vfio_vga_probe_nvidia_3d0_quirk()
680 data, "vfio-nvidia-3d4-quirk", 2); in vfio_vga_probe_nvidia_3d0_quirk()
681 memory_region_add_subregion(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, in vfio_vga_probe_nvidia_3d0_quirk()
682 0x14 /* 0x3c0 + 0x14 */, &quirk->mem[0]); in vfio_vga_probe_nvidia_3d0_quirk()
684 memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_nvidia_3d0_quirk, in vfio_vga_probe_nvidia_3d0_quirk()
685 data, "vfio-nvidia-3d0-quirk", 2); in vfio_vga_probe_nvidia_3d0_quirk()
686 memory_region_add_subregion(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, in vfio_vga_probe_nvidia_3d0_quirk()
687 0x10 /* 0x3c0 + 0x10 */, &quirk->mem[1]); in vfio_vga_probe_nvidia_3d0_quirk()
689 QLIST_INSERT_HEAD(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks, in vfio_vga_probe_nvidia_3d0_quirk()
692 trace_vfio_quirk_nvidia_3d0_probe(vdev->vbasedev.name); in vfio_vga_probe_nvidia_3d0_quirk()
713 VFIOPCIDevice *vdev = bar5->window.vdev; in vfio_nvidia_bar5_enable()
715 if (((bar5->master & bar5->enable) & 0x1) == bar5->enabled) { in vfio_nvidia_bar5_enable()
719 bar5->enabled = !bar5->enabled; in vfio_nvidia_bar5_enable()
720 trace_vfio_quirk_nvidia_bar5_state(vdev->vbasedev.name, in vfio_nvidia_bar5_enable()
721 bar5->enabled ? "Enable" : "Disable"); in vfio_nvidia_bar5_enable()
722 memory_region_set_enabled(bar5->addr_mem, bar5->enabled); in vfio_nvidia_bar5_enable()
723 memory_region_set_enabled(bar5->data_mem, bar5->enabled); in vfio_nvidia_bar5_enable()
730 VFIOPCIDevice *vdev = bar5->window.vdev; in vfio_nvidia_bar5_quirk_master_read()
732 return vfio_region_read(&vdev->bars[5].region, addr, size); in vfio_nvidia_bar5_quirk_master_read()
739 VFIOPCIDevice *vdev = bar5->window.vdev; in vfio_nvidia_bar5_quirk_master_write()
741 vfio_region_write(&vdev->bars[5].region, addr, data, size); in vfio_nvidia_bar5_quirk_master_write()
743 bar5->master = data; in vfio_nvidia_bar5_quirk_master_write()
757 VFIOPCIDevice *vdev = bar5->window.vdev; in vfio_nvidia_bar5_quirk_enable_read()
759 return vfio_region_read(&vdev->bars[5].region, addr + 4, size); in vfio_nvidia_bar5_quirk_enable_read()
766 VFIOPCIDevice *vdev = bar5->window.vdev; in vfio_nvidia_bar5_quirk_enable_write()
768 vfio_region_write(&vdev->bars[5].region, addr + 4, data, size); in vfio_nvidia_bar5_quirk_enable_write()
770 bar5->enable = data; in vfio_nvidia_bar5_quirk_enable_write()
786 if (vdev->no_geforce_quirks || in vfio_probe_nvidia_bar5_quirk()
788 !vdev->vga || nr != 5 || !vdev->bars[5].ioport) { in vfio_probe_nvidia_bar5_quirk()
793 bar5 = quirk->data = g_malloc0(sizeof(*bar5) + in vfio_probe_nvidia_bar5_quirk()
795 window = &bar5->window; in vfio_probe_nvidia_bar5_quirk()
797 window->vdev = vdev; in vfio_probe_nvidia_bar5_quirk()
798 window->address_offset = 0x8; in vfio_probe_nvidia_bar5_quirk()
799 window->data_offset = 0xc; in vfio_probe_nvidia_bar5_quirk()
800 window->nr_matches = 2; in vfio_probe_nvidia_bar5_quirk()
801 window->matches[0].match = 0x1800; in vfio_probe_nvidia_bar5_quirk()
802 window->matches[0].mask = PCI_CONFIG_SPACE_SIZE - 1; in vfio_probe_nvidia_bar5_quirk()
803 window->matches[1].match = 0x88000; in vfio_probe_nvidia_bar5_quirk()
804 window->matches[1].mask = vdev->config_size - 1; in vfio_probe_nvidia_bar5_quirk()
805 window->bar = nr; in vfio_probe_nvidia_bar5_quirk()
806 window->addr_mem = bar5->addr_mem = &quirk->mem[0]; in vfio_probe_nvidia_bar5_quirk()
807 window->data_mem = bar5->data_mem = &quirk->mem[1]; in vfio_probe_nvidia_bar5_quirk()
809 memory_region_init_io(window->addr_mem, OBJECT(vdev), in vfio_probe_nvidia_bar5_quirk()
811 "vfio-nvidia-bar5-window-address-quirk", 4); in vfio_probe_nvidia_bar5_quirk()
812 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar5_quirk()
813 window->address_offset, in vfio_probe_nvidia_bar5_quirk()
814 window->addr_mem, 1); in vfio_probe_nvidia_bar5_quirk()
815 memory_region_set_enabled(window->addr_mem, false); in vfio_probe_nvidia_bar5_quirk()
817 memory_region_init_io(window->data_mem, OBJECT(vdev), in vfio_probe_nvidia_bar5_quirk()
819 "vfio-nvidia-bar5-window-data-quirk", 4); in vfio_probe_nvidia_bar5_quirk()
820 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar5_quirk()
821 window->data_offset, in vfio_probe_nvidia_bar5_quirk()
822 window->data_mem, 1); in vfio_probe_nvidia_bar5_quirk()
823 memory_region_set_enabled(window->data_mem, false); in vfio_probe_nvidia_bar5_quirk()
825 memory_region_init_io(&quirk->mem[2], OBJECT(vdev), in vfio_probe_nvidia_bar5_quirk()
827 "vfio-nvidia-bar5-master-quirk", 4); in vfio_probe_nvidia_bar5_quirk()
828 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar5_quirk()
829 0, &quirk->mem[2], 1); in vfio_probe_nvidia_bar5_quirk()
831 memory_region_init_io(&quirk->mem[3], OBJECT(vdev), in vfio_probe_nvidia_bar5_quirk()
833 "vfio-nvidia-bar5-enable-quirk", 4); in vfio_probe_nvidia_bar5_quirk()
834 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar5_quirk()
835 4, &quirk->mem[3], 1); in vfio_probe_nvidia_bar5_quirk()
837 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_nvidia_bar5_quirk()
839 trace_vfio_quirk_nvidia_bar5_probe(vdev->vbasedev.name); in vfio_probe_nvidia_bar5_quirk()
862 VFIOPCIDevice *vdev = mirror->vdev; in vfio_nvidia_quirk_mirror_write()
863 PCIDevice *pdev = &vdev->pdev; in vfio_nvidia_quirk_mirror_write()
864 LastDataSet *last = (LastDataSet *)&mirror->data; in vfio_nvidia_quirk_mirror_write()
871 * read-only, so we allow writes covering either of those to real hw. in vfio_nvidia_quirk_mirror_write()
873 if ((pdev->cap_present & QEMU_PCI_CAP_MSI) && in vfio_nvidia_quirk_mirror_write()
874 vfio_range_contained(addr, size, pdev->msi_cap, PCI_MSI_FLAGS)) { in vfio_nvidia_quirk_mirror_write()
875 vfio_region_write(&vdev->bars[mirror->bar].region, in vfio_nvidia_quirk_mirror_write()
876 addr + mirror->offset, data, size); in vfio_nvidia_quirk_mirror_write()
877 trace_vfio_quirk_nvidia_bar0_msi_ack(vdev->vbasedev.name); in vfio_nvidia_quirk_mirror_write()
883 * primarily expected to accelerate the MSI-ACK behavior, such as noted in vfio_nvidia_quirk_mirror_write()
888 * MSI-ACK region. Note that as some writes are bypassed via the ioeventfd, in vfio_nvidia_quirk_mirror_write()
895 if (!vdev->no_kvm_ioeventfd && in vfio_nvidia_quirk_mirror_write()
896 addr >= PCI_STD_HEADER_SIZEOF && last->added <= MAX_DYN_IOEVENTFD) { in vfio_nvidia_quirk_mirror_write()
897 if (addr != last->addr || data != last->data || size != last->size) { in vfio_nvidia_quirk_mirror_write()
898 last->addr = addr; in vfio_nvidia_quirk_mirror_write()
899 last->data = data; in vfio_nvidia_quirk_mirror_write()
900 last->size = size; in vfio_nvidia_quirk_mirror_write()
901 last->hits = 1; in vfio_nvidia_quirk_mirror_write()
902 } else if (++last->hits >= HITS_FOR_IOEVENTFD) { in vfio_nvidia_quirk_mirror_write()
903 if (last->added < MAX_DYN_IOEVENTFD) { in vfio_nvidia_quirk_mirror_write()
905 ioeventfd = vfio_ioeventfd_init(vdev, mirror->mem, addr, size, in vfio_nvidia_quirk_mirror_write()
906 data, &vdev->bars[mirror->bar].region, in vfio_nvidia_quirk_mirror_write()
907 mirror->offset + addr, true); in vfio_nvidia_quirk_mirror_write()
909 VFIOQuirk *quirk = last->quirk; in vfio_nvidia_quirk_mirror_write()
911 QLIST_INSERT_HEAD(&quirk->ioeventfds, ioeventfd, next); in vfio_nvidia_quirk_mirror_write()
912 last->added++; in vfio_nvidia_quirk_mirror_write()
915 last->added++; in vfio_nvidia_quirk_mirror_write()
918 "size %u", vdev->vbasedev.name, addr, data, size); in vfio_nvidia_quirk_mirror_write()
932 VFIOConfigMirrorQuirk *mirror = quirk->data; in vfio_nvidia_bar0_quirk_reset()
933 LastDataSet *last = (LastDataSet *)&mirror->data; in vfio_nvidia_bar0_quirk_reset()
935 last->addr = last->data = last->size = last->hits = last->added = 0; in vfio_nvidia_bar0_quirk_reset()
946 if (vdev->no_geforce_quirks || in vfio_probe_nvidia_bar0_quirk()
953 quirk->reset = vfio_nvidia_bar0_quirk_reset; in vfio_probe_nvidia_bar0_quirk()
954 mirror = quirk->data = g_malloc0(sizeof(*mirror) + sizeof(LastDataSet)); in vfio_probe_nvidia_bar0_quirk()
955 mirror->mem = quirk->mem; in vfio_probe_nvidia_bar0_quirk()
956 mirror->vdev = vdev; in vfio_probe_nvidia_bar0_quirk()
957 mirror->offset = 0x88000; in vfio_probe_nvidia_bar0_quirk()
958 mirror->bar = nr; in vfio_probe_nvidia_bar0_quirk()
959 last = (LastDataSet *)&mirror->data; in vfio_probe_nvidia_bar0_quirk()
960 last->quirk = quirk; in vfio_probe_nvidia_bar0_quirk()
962 memory_region_init_io(mirror->mem, OBJECT(vdev), in vfio_probe_nvidia_bar0_quirk()
964 "vfio-nvidia-bar0-88000-mirror-quirk", in vfio_probe_nvidia_bar0_quirk()
965 vdev->config_size); in vfio_probe_nvidia_bar0_quirk()
966 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar0_quirk()
967 mirror->offset, mirror->mem, 1); in vfio_probe_nvidia_bar0_quirk()
969 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_nvidia_bar0_quirk()
972 if (vdev->vga) { in vfio_probe_nvidia_bar0_quirk()
974 quirk->reset = vfio_nvidia_bar0_quirk_reset; in vfio_probe_nvidia_bar0_quirk()
975 mirror = quirk->data = g_malloc0(sizeof(*mirror) + sizeof(LastDataSet)); in vfio_probe_nvidia_bar0_quirk()
976 mirror->mem = quirk->mem; in vfio_probe_nvidia_bar0_quirk()
977 mirror->vdev = vdev; in vfio_probe_nvidia_bar0_quirk()
978 mirror->offset = 0x1800; in vfio_probe_nvidia_bar0_quirk()
979 mirror->bar = nr; in vfio_probe_nvidia_bar0_quirk()
980 last = (LastDataSet *)&mirror->data; in vfio_probe_nvidia_bar0_quirk()
981 last->quirk = quirk; in vfio_probe_nvidia_bar0_quirk()
983 memory_region_init_io(mirror->mem, OBJECT(vdev), in vfio_probe_nvidia_bar0_quirk()
985 "vfio-nvidia-bar0-1800-mirror-quirk", in vfio_probe_nvidia_bar0_quirk()
987 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_nvidia_bar0_quirk()
988 mirror->offset, mirror->mem, 1); in vfio_probe_nvidia_bar0_quirk()
990 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_nvidia_bar0_quirk()
993 trace_vfio_quirk_nvidia_bar0_probe(vdev->vbasedev.name); in vfio_probe_nvidia_bar0_quirk()
997 * TODO - Some Nvidia devices provide config access to their companion HDA
1005 * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2
1007 * register. According to the Linux r8169 driver, the MSI-X table is addressed
1011 * ignore because the MSI-X table should always be accessed as a dword (full
1016 * Read from MSI-X table offset 0
1021 * Write 0xfee00000 to MSI-X table offset 0
1037 VFIOPCIDevice *vdev = rtl->vdev; in vfio_rtl8168_quirk_address_read()
1038 uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x74, size); in vfio_rtl8168_quirk_address_read()
1040 if (rtl->enabled) { in vfio_rtl8168_quirk_address_read()
1041 data = rtl->addr ^ 0x80000000U; /* latch/complete */ in vfio_rtl8168_quirk_address_read()
1042 trace_vfio_quirk_rtl8168_fake_latch(vdev->vbasedev.name, data); in vfio_rtl8168_quirk_address_read()
1052 VFIOPCIDevice *vdev = rtl->vdev; in vfio_rtl8168_quirk_address_write()
1054 rtl->enabled = false; in vfio_rtl8168_quirk_address_write()
1056 if ((data & 0x7fff0000) == 0x10000) { /* MSI-X table */ in vfio_rtl8168_quirk_address_write()
1057 rtl->enabled = true; in vfio_rtl8168_quirk_address_write()
1058 rtl->addr = (uint32_t)data; in vfio_rtl8168_quirk_address_write()
1061 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX) { in vfio_rtl8168_quirk_address_write()
1063 uint64_t val = rtl->data; in vfio_rtl8168_quirk_address_write()
1065 trace_vfio_quirk_rtl8168_msix_write(vdev->vbasedev.name, in vfio_rtl8168_quirk_address_write()
1068 /* Write to the proper guest MSI-X table instead */ in vfio_rtl8168_quirk_address_write()
1069 memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, in vfio_rtl8168_quirk_address_write()
1074 return; /* Do not write guest MSI-X data to hardware */ in vfio_rtl8168_quirk_address_write()
1078 vfio_region_write(&vdev->bars[2].region, addr + 0x74, data, size); in vfio_rtl8168_quirk_address_write()
1096 VFIOPCIDevice *vdev = rtl->vdev; in vfio_rtl8168_quirk_data_read()
1097 uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x70, size); in vfio_rtl8168_quirk_data_read()
1099 if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { in vfio_rtl8168_quirk_data_read()
1100 hwaddr offset = rtl->addr & 0xfff; in vfio_rtl8168_quirk_data_read()
1101 memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset, in vfio_rtl8168_quirk_data_read()
1104 trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data); in vfio_rtl8168_quirk_data_read()
1114 VFIOPCIDevice *vdev = rtl->vdev; in vfio_rtl8168_quirk_data_write()
1116 rtl->data = (uint32_t)data; in vfio_rtl8168_quirk_data_write()
1118 vfio_region_write(&vdev->bars[2].region, addr + 0x70, data, size); in vfio_rtl8168_quirk_data_write()
1142 quirk->data = rtl = g_malloc0(sizeof(*rtl)); in vfio_probe_rtl8168_bar2_quirk()
1143 rtl->vdev = vdev; in vfio_probe_rtl8168_bar2_quirk()
1145 memory_region_init_io(&quirk->mem[0], OBJECT(vdev), in vfio_probe_rtl8168_bar2_quirk()
1147 "vfio-rtl8168-window-address-quirk", 4); in vfio_probe_rtl8168_bar2_quirk()
1148 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_rtl8168_bar2_quirk()
1149 0x74, &quirk->mem[0], 1); in vfio_probe_rtl8168_bar2_quirk()
1151 memory_region_init_io(&quirk->mem[1], OBJECT(vdev), in vfio_probe_rtl8168_bar2_quirk()
1153 "vfio-rtl8168-window-data-quirk", 4); in vfio_probe_rtl8168_bar2_quirk()
1154 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_rtl8168_bar2_quirk()
1155 0x70, &quirk->mem[1], 1); in vfio_probe_rtl8168_bar2_quirk()
1157 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); in vfio_probe_rtl8168_bar2_quirk()
1159 trace_vfio_quirk_rtl8168_probe(vdev->vbasedev.name); in vfio_probe_rtl8168_bar2_quirk()
1177 vdev->igd_opregion = g_malloc0(info->size); in vfio_pci_igd_opregion_init()
1178 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, in vfio_pci_igd_opregion_init()
1179 info->size, info->offset); in vfio_pci_igd_opregion_init()
1180 if (ret != info->size) { in vfio_pci_igd_opregion_init()
1182 g_free(vdev->igd_opregion); in vfio_pci_igd_opregion_init()
1183 vdev->igd_opregion = NULL; in vfio_pci_igd_opregion_init()
1200 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", in vfio_pci_igd_opregion_init()
1201 vdev->igd_opregion, info->size); in vfio_pci_igd_opregion_init()
1203 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); in vfio_pci_igd_opregion_init()
1205 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); in vfio_pci_igd_opregion_init()
1206 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); in vfio_pci_igd_opregion_init()
1207 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); in vfio_pci_igd_opregion_init()
1226 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { in vfio_vga_quirk_exit()
1227 QLIST_FOREACH(quirk, &vdev->vga->region[i].quirks, next) { in vfio_vga_quirk_exit()
1228 for (j = 0; j < quirk->nr_mem; j++) { in vfio_vga_quirk_exit()
1229 memory_region_del_subregion(&vdev->vga->region[i].mem, in vfio_vga_quirk_exit()
1230 &quirk->mem[j]); in vfio_vga_quirk_exit()
1240 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { in vfio_vga_quirk_finalize()
1241 while (!QLIST_EMPTY(&vdev->vga->region[i].quirks)) { in vfio_vga_quirk_finalize()
1242 VFIOQuirk *quirk = QLIST_FIRST(&vdev->vga->region[i].quirks); in vfio_vga_quirk_finalize()
1244 for (j = 0; j < quirk->nr_mem; j++) { in vfio_vga_quirk_finalize()
1245 object_unparent(OBJECT(&quirk->mem[j])); in vfio_vga_quirk_finalize()
1247 g_free(quirk->mem); in vfio_vga_quirk_finalize()
1248 g_free(quirk->data); in vfio_vga_quirk_finalize()
1269 VFIOBAR *bar = &vdev->bars[nr]; in vfio_bar_quirk_exit()
1273 QLIST_FOREACH(quirk, &bar->quirks, next) { in vfio_bar_quirk_exit()
1274 while (!QLIST_EMPTY(&quirk->ioeventfds)) { in vfio_bar_quirk_exit()
1275 vfio_ioeventfd_exit(vdev, QLIST_FIRST(&quirk->ioeventfds)); in vfio_bar_quirk_exit()
1278 for (i = 0; i < quirk->nr_mem; i++) { in vfio_bar_quirk_exit()
1279 memory_region_del_subregion(bar->region.mem, &quirk->mem[i]); in vfio_bar_quirk_exit()
1286 VFIOBAR *bar = &vdev->bars[nr]; in vfio_bar_quirk_finalize()
1289 while (!QLIST_EMPTY(&bar->quirks)) { in vfio_bar_quirk_finalize()
1290 VFIOQuirk *quirk = QLIST_FIRST(&bar->quirks); in vfio_bar_quirk_finalize()
1292 for (i = 0; i < quirk->nr_mem; i++) { in vfio_bar_quirk_finalize()
1293 object_unparent(OBJECT(&quirk->mem[i])); in vfio_bar_quirk_finalize()
1295 g_free(quirk->mem); in vfio_bar_quirk_finalize()
1296 g_free(quirk->data); in vfio_bar_quirk_finalize()
1310 VFIOBAR *bar = &vdev->bars[i]; in vfio_quirk_reset()
1312 QLIST_FOREACH(quirk, &bar->quirks, next) { in vfio_quirk_reset()
1313 if (quirk->reset) { in vfio_quirk_reset()
1314 quirk->reset(vdev, quirk); in vfio_quirk_reset()
1349 vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4); in vfio_radeon_smc_is_running()
1350 clk = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_smc_is_running()
1351 vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000370, 4); in vfio_radeon_smc_is_running()
1352 pc_c = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_smc_is_running()
1370 vfio_region_write(&vdev->bars[5].region, 0x200, 0xc00c0000, 4); in vfio_radeon_set_gfx_only_reset()
1371 fuse = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_set_gfx_only_reset()
1374 vfio_region_write(&vdev->bars[5].region, 0x200, 0xc0000010, 4); in vfio_radeon_set_gfx_only_reset()
1375 misc = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_set_gfx_only_reset()
1379 vfio_region_write(&vdev->bars[5].region, 0x204, misc ^ 2, 4); in vfio_radeon_set_gfx_only_reset()
1380 vfio_region_read(&vdev->bars[5].region, 0x204, 4); /* flush */ in vfio_radeon_set_gfx_only_reset()
1386 PCIDevice *pdev = &vdev->pdev; in vfio_radeon_reset()
1391 if (vdev->vbasedev.reset_works) { in vfio_radeon_reset()
1392 trace_vfio_quirk_ati_bonaire_reset_skipped(vdev->vbasedev.name); in vfio_radeon_reset()
1393 return -ENODEV; in vfio_radeon_reset()
1401 ret = -EINVAL; in vfio_radeon_reset()
1402 trace_vfio_quirk_ati_bonaire_reset_no_smc(vdev->vbasedev.name); in vfio_radeon_reset()
1415 if (vfio_region_read(&vdev->bars[5].region, 0x5428, 4) != 0xffffffff) { in vfio_radeon_reset()
1421 trace_vfio_quirk_ati_bonaire_reset_timeout(vdev->vbasedev.name); in vfio_radeon_reset()
1425 vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000000, 4); in vfio_radeon_reset()
1426 data = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_reset()
1428 vfio_region_write(&vdev->bars[5].region, 0x204, data, 4); in vfio_radeon_reset()
1431 vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4); in vfio_radeon_reset()
1432 data = vfio_region_read(&vdev->bars[5].region, 0x204, 4); in vfio_radeon_reset()
1434 vfio_region_write(&vdev->bars[5].region, 0x204, data, 4); in vfio_radeon_reset()
1436 trace_vfio_quirk_ati_bonaire_reset_done(vdev->vbasedev.name); in vfio_radeon_reset()
1447 switch (vdev->vendor_id) { in vfio_setup_resetfn_quirk()
1449 switch (vdev->device_id) { in vfio_setup_resetfn_quirk()
1470 vdev->resetfn = vfio_radeon_reset; in vfio_setup_resetfn_quirk()
1471 trace_vfio_quirk_ati_bonaire_reset(vdev->vbasedev.name); in vfio_setup_resetfn_quirk()
1487 * +----------------+----------------+----------------+----------------+
1489 * +----------------+----------------+----------------+----------------+
1491 * +---------------------------------+---------------------------------+
1493 * https://lists.gnu.org/archive/html/qemu-devel/2017-08/pdfUda5iEpgOS.pdf
1496 * https://lists.gnu.org/archive/html/qemu-devel/2023-06/pdf142OR4O4c2.pdf
1520 error_setg(errp, "Property %s: valid range 0-15", name); in set_nv_gpudirect_clique_id()
1529 .description = "NVIDIA GPUDirect Clique ID (0 - 15)",
1537 pos <= (PCI_CFG_SPACE_SIZE - PCI_CAP_SIZEOF)); in is_valid_std_cap_offset()
1543 PCIDevice *pdev = &vdev->pdev; in vfio_add_nv_gpudirect_cap()
1548 if (vdev->nv_gpudirect_clique == 0xFF) { in vfio_add_nv_gpudirect_cap()
1557 if (pci_get_byte(pdev->config + PCI_CLASS_DEVICE + 1) != in vfio_add_nv_gpudirect_cap()
1566 * MSI-X capability at C8h. We don't know how to determine the GPU in vfio_add_nv_gpudirect_cap()
1570 * NB. Cap list head in pdev->config is already cleared, read from device. in vfio_add_nv_gpudirect_cap()
1572 ret = pread(vdev->vbasedev.fd, &tmp, 1, in vfio_add_nv_gpudirect_cap()
1573 vdev->config_offset + PCI_CAPABILITY_LIST); in vfio_add_nv_gpudirect_cap()
1585 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]; in vfio_add_nv_gpudirect_cap()
1603 memset(vdev->emulated_config_bits + pos, 0xFF, 8); in vfio_add_nv_gpudirect_cap()
1605 pci_set_byte(pdev->config + pos++, 8); in vfio_add_nv_gpudirect_cap()
1606 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1607 pci_set_byte(pdev->config + pos++, '2'); in vfio_add_nv_gpudirect_cap()
1608 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1609 pci_set_byte(pdev->config + pos++, vdev->nv_gpudirect_clique << 3); in vfio_add_nv_gpudirect_cap()
1610 pci_set_byte(pdev->config + pos, 0); in vfio_add_nv_gpudirect_cap()
1617 * kernel performs enumeration of the VMD sub-device domain. Guest transactions
1618 * to VMD sub-devices go through MMU translation from guest addresses to
1626 * shadow registers in a vendor-specific capability register for devices
1627 * without native support. The position of 0xE8-0xFF is in the reserved range
1646 ret = pread(vdev->vbasedev.fd, membar_phys, 16, in vfio_add_vmd_shadow_cap()
1647 vdev->config_offset + PCI_BASE_ADDRESS_2); in vfio_add_vmd_shadow_cap()
1650 vdev->vbasedev.name, ret); in vfio_add_vmd_shadow_cap()
1654 ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, in vfio_add_vmd_shadow_cap()
1661 memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); in vfio_add_vmd_shadow_cap()
1663 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_LEN); in vfio_add_vmd_shadow_cap()
1664 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_VER); in vfio_add_vmd_shadow_cap()
1665 pci_set_long(vdev->pdev.config + pos, 0x53484457); /* SHDW */ in vfio_add_vmd_shadow_cap()
1666 memcpy(vdev->pdev.config + pos + 4, membar_phys, 16); in vfio_add_vmd_shadow_cap()