110     return vfio_region_read(&vdev->bars[window->bar].region,  in vfio_generic_window_quirk_address_read()
124     vfio_region_write(&vdev->bars[window->bar].region,  in vfio_generic_window_quirk_address_write()
152     data = vfio_region_read(&vdev->bars[window->bar].region,  in vfio_generic_window_quirk_data_read()
177     vfio_region_write(&vdev->bars[window->bar].region,  in vfio_generic_window_quirk_data_write()
209     (void)vfio_region_read(&vdev->bars[mirror->bar].region,  in vfio_generic_quirk_mirror_read()
418         !vdev->bars[4].ioport || vdev->bars[4].region.size < 256) {  in vfio_vga_probe_ati_3c3_quirk()
471     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_ati_bar4_quirk()
478     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_ati_bar4_quirk()
482     QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_ati_bar4_quirk()
497         !vdev->vga || nr != 2 || !vdev->bars[2].mem64) {  in vfio_probe_ati_bar2_quirk()
511     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_ati_bar2_quirk()
514     QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_ati_bar2_quirk()
671         !vdev->bars[1].region.size) {  in vfio_vga_probe_nvidia_3d0_quirk()
697  * a set of address/data ports to the MMIO BARs.  The BAR we care about is
732     return vfio_region_read(&vdev->bars[5].region, addr, size);  in vfio_nvidia_bar5_quirk_master_read()
741     vfio_region_write(&vdev->bars[5].region, addr, data, size);  in vfio_nvidia_bar5_quirk_master_write()
759     return vfio_region_read(&vdev->bars[5].region, addr + 4, size);  in vfio_nvidia_bar5_quirk_enable_read()
768     vfio_region_write(&vdev->bars[5].region, addr + 4, data, size);  in vfio_nvidia_bar5_quirk_enable_write()
788         !vdev->vga || nr != 5 || !vdev->bars[5].ioport) {  in vfio_probe_nvidia_bar5_quirk()
812     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar5_quirk()
820     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar5_quirk()
828     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar5_quirk()
834     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar5_quirk()
837     QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_nvidia_bar5_quirk()
875         vfio_region_write(&vdev->bars[mirror->bar].region,  in vfio_nvidia_quirk_mirror_write()
906                                         data, &vdev->bars[mirror->bar].region,  in vfio_nvidia_quirk_mirror_write()
966     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar0_quirk()
969     QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_nvidia_bar0_quirk()
987         memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_nvidia_bar0_quirk()
990         QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_nvidia_bar0_quirk()
1038     uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x74, size);  in vfio_rtl8168_quirk_address_read()
1078     vfio_region_write(&vdev->bars[2].region, addr + 0x74, data, size);  in vfio_rtl8168_quirk_address_write()
1097     uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x70, size);  in vfio_rtl8168_quirk_data_read()
1118     vfio_region_write(&vdev->bars[2].region, addr + 0x70, data, size);  in vfio_rtl8168_quirk_data_write()
1148     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_rtl8168_bar2_quirk()
1154     memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,  in vfio_probe_rtl8168_bar2_quirk()
1157     QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);  in vfio_probe_rtl8168_bar2_quirk()
1269     VFIOBAR *bar = &vdev->bars[nr];  in vfio_bar_quirk_exit()
1286     VFIOBAR *bar = &vdev->bars[nr];  in vfio_bar_quirk_finalize()
1310         VFIOBAR *bar = &vdev->bars[i];  in vfio_quirk_reset()
1349     vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4);  in vfio_radeon_smc_is_running()
1350     clk = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_smc_is_running()
1351     vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000370, 4);  in vfio_radeon_smc_is_running()
1352     pc_c = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_smc_is_running()
1370     vfio_region_write(&vdev->bars[5].region, 0x200, 0xc00c0000, 4);  in vfio_radeon_set_gfx_only_reset()
1371     fuse = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_set_gfx_only_reset()
1374     vfio_region_write(&vdev->bars[5].region, 0x200, 0xc0000010, 4);  in vfio_radeon_set_gfx_only_reset()
1375     misc = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_set_gfx_only_reset()
1379         vfio_region_write(&vdev->bars[5].region, 0x204, misc ^ 2, 4);  in vfio_radeon_set_gfx_only_reset()
1380         vfio_region_read(&vdev->bars[5].region, 0x204, 4); /* flush */  in vfio_radeon_set_gfx_only_reset()
1415         if (vfio_region_read(&vdev->bars[5].region, 0x5428, 4) != 0xffffffff) {  in vfio_radeon_reset()
1425     vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000000, 4);  in vfio_radeon_reset()
1426     data = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_reset()
1428     vfio_region_write(&vdev->bars[5].region, 0x204, data, 4);  in vfio_radeon_reset()
1431     vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4);  in vfio_radeon_reset()
1432     data = vfio_region_read(&vdev->bars[5].region, 0x204, 4);  in vfio_radeon_reset()
1434     vfio_region_write(&vdev->bars[5].region, 0x204, data, 4);  in vfio_radeon_reset()