62     if ((vdev->device_id & 0xfff) == 0xa84) {  in igd_gen()
66     switch (vdev->device_id & 0xff00) {  in igd_gen()
68     case 0x0000:  in igd_gen()
69     case 0x2500:  in igd_gen()
70     case 0x2700:  in igd_gen()
71     case 0x2900:  in igd_gen()
72     case 0x2a00:  in igd_gen()
73     case 0x2e00:  in igd_gen()
74     case 0x3500:  in igd_gen()
75     case 0xa000:  in igd_gen()
78     case 0x0100:  in igd_gen()
79     case 0x0400:  in igd_gen()
80     case 0x0a00:  in igd_gen()
81     case 0x0c00:  in igd_gen()
82     case 0x0d00:  in igd_gen()
83     case 0x0f00:  in igd_gen()
86     case 0x1600:  in igd_gen()
87     case 0x1900:  in igd_gen()
88     case 0x2200:  in igd_gen()
89     case 0x5900:  in igd_gen()
92     case 0x3e00:  in igd_gen()
95     case 0x4500:  in igd_gen()
98     case 0x9A00:  in igd_gen()
115 #define IGD_GMCH 0x50 /* Graphics Control Register */
116 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */
117 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */
153     for (i = 0; i < len; i++) {  in vfio_pci_igd_copy()
162     return 0;  in vfio_pci_igd_copy()
176     host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0));  in vfio_pci_igd_host_init()
200     if (pdev->devfn != PCI_DEVFN(0x1f, 0)) {  in vfio_pci_igd_lpc_bridge_realize()
201         error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0");  in vfio_pci_igd_lpc_bridge_realize()
241                                  0, PCI_DEVFN(0x1f, 0));  in type_init()
244                                  PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge");  in type_init()
270     ggms = (gmch >> (gen < 8 ? 8 : 6)) & 0x3;  in vfio_igd_gtt_max()
297     igd->index = ~0;  in vfio_igd_quirk_data_read()
311      * Programming the GGMS starts at index 0x1 and uses every 4th index (ie.  in vfio_igd_quirk_data_write()
312      * 0x1, 0x5, 0x9, 0xd,...).  For pre-Gen8 each 4-byte write is a whole PTE  in vfio_igd_quirk_data_write()
313      * entry, with 0th bit enable set.  For Gen8 and up, PTEs are 64bit, so  in vfio_igd_quirk_data_write()
314      * entries 0x5 & 0xd are the high dword, in our case zero.  Each PTE points  in vfio_igd_quirk_data_write()
340             val = 0; /* upper 32bits of pte, we only enable below 4G PTEs */  in vfio_igd_quirk_data_write()
349     igd->index = ~0;  in vfio_igd_quirk_data_write()
364     igd->index = ~0;  in vfio_igd_quirk_index_read()
386 #define IGD_BDSM_MMIO_OFFSET 0x1080C0
410     return 0;  in vfio_igd_quirk_bdsm_read()
457         !vfio_is_vga(vdev) || nr != 0 ||  in vfio_probe_igd_bar0_quirk()
459                                        0, PCI_DEVFN(0x2, 0))) {  in vfio_probe_igd_bar0_quirk()
475     memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_bdsm_quirk,  in vfio_probe_igd_bar0_quirk()
477     memory_region_add_subregion_overlap(vdev->bars[0].region.mem,  in vfio_probe_igd_bar0_quirk()
478                                         IGD_BDSM_MMIO_OFFSET, &quirk->mem[0],  in vfio_probe_igd_bar0_quirk()
489         gms = (gmch >> 3) & 0x1f;  in igd_get_stolen_mb()
491         gms = (gmch >> 8) & 0xff;  in igd_get_stolen_mb()
495         if (gms > 0x10) {  in igd_get_stolen_mb()
496             error_report("Unsupported IGD GMS value 0x%x", gms);  in igd_get_stolen_mb()
497             return 0;  in igd_get_stolen_mb()
501         if (gms < 0xf0)  in igd_get_stolen_mb()
504             return (gms - 0xf0) * 4 + 4;  in igd_get_stolen_mb()
517     int i, ret, ggms_mb, gms_mb = 0, gen;  in vfio_probe_igd_bar4_quirk()
531                                        0, PCI_DEVFN(0x2, 0))) {  in vfio_probe_igd_bar4_quirk()
536      * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we  in vfio_probe_igd_bar4_quirk()
541                                  0, PCI_DEVFN(0x1f, 0));  in vfio_probe_igd_bar4_quirk()
545                      "devices at address 1f.0", vdev->vbasedev.name);  in vfio_probe_igd_bar4_quirk()
623     if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) {  in vfio_probe_igd_bar4_quirk()
657     igd->index = ~0;  in vfio_probe_igd_bar4_quirk()
667     memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk,  in vfio_probe_igd_bar4_quirk()
670                                         0, &quirk->mem[0], 1);  in vfio_probe_igd_bar4_quirk()
680     ggms_mb = (gmch >> (gen < 8 ? 8 : 6)) & 0x3;  in vfio_probe_igd_bar4_quirk()
693      * config offset 0x5C.  in vfio_probe_igd_bar4_quirk()
702     pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0);  in vfio_probe_igd_bar4_quirk()
703     pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0);  in vfio_probe_igd_bar4_quirk()
707         pci_set_long(vdev->pdev.config + IGD_BDSM, 0);  in vfio_probe_igd_bar4_quirk()
708         pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0);  in vfio_probe_igd_bar4_quirk()
709         pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0);  in vfio_probe_igd_bar4_quirk()
711         pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0);  in vfio_probe_igd_bar4_quirk()
712         pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0);  in vfio_probe_igd_bar4_quirk()
713         pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0);  in vfio_probe_igd_bar4_quirk()
737         vfio_region_write(&vdev->bars[4].region, 0, i, 4);  in vfio_probe_igd_bar4_quirk()
738         vfio_region_write(&vdev->bars[4].region, 4, 0, 4);  in vfio_probe_igd_bar4_quirk()