Lines Matching refs:TUSB_SYS_REG_BASE
85 #define TUSB_SYS_REG_BASE 0x800 macro
87 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
93 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
94 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
118 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
130 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
133 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
136 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
141 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
158 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
159 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
160 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
176 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
177 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
178 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
179 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
180 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
181 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
182 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
183 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
184 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
185 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
186 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
187 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
188 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
189 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
190 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
191 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
194 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
195 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
196 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
197 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
216 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
217 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
218 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
219 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
220 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
221 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c)
222 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
223 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c)
224 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188)
225 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
226 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
227 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
229 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
230 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)