76     struct xlx_timer *timers;  member
86     /* Timers get a 4x32bit control reg area each.  */  in timer_from_addr()
96         csr = t->timers[i].regs[R_TCSR];  in timer_update_irq()
100     /* All timers within the same slave share a single IRQ line.  */  in timer_update_irq()
114     xt = &t->timers[timer];  in timer_read()
115     /* Further decoding to address a specific timers reg.  */  in timer_read()
165     xt = &t->timers[timer];  in timer_write()
168     /* Further decoding to address a specific timers reg.  */  in timer_write()
220     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));  in xilinx_timer_realize()
222         struct xlx_timer *xt = &t->timers[i];  in xilinx_timer_realize()
241     /* All timers share a single irq line.  */  in xilinx_timer_init()