Lines Matching refs:value
276 uint32_t value = val64; in sifive_pwm_write() local
281 trace_sifive_pwm_write(value, addr); in sifive_pwm_write()
285 if (value & (R_CONFIG_CMP0CENTER_MASK | R_CONFIG_CMP1CENTER_MASK | in sifive_pwm_write()
291 if (value & (R_CONFIG_CMP0GANG_MASK | R_CONFIG_CMP1GANG_MASK | in sifive_pwm_write()
297 if (value & (R_CONFIG_CMP0IP_MASK | R_CONFIG_CMP1IP_MASK | in sifive_pwm_write()
303 if (!(value & R_CONFIG_CMP0IP_MASK)) { in sifive_pwm_write()
307 if (!(value & R_CONFIG_CMP1IP_MASK)) { in sifive_pwm_write()
311 if (!(value & R_CONFIG_CMP2IP_MASK)) { in sifive_pwm_write()
315 if (!(value & R_CONFIG_CMP3IP_MASK)) { in sifive_pwm_write()
326 if ((!HAS_PWM_EN_BITS(s->pwmcfg) && HAS_PWM_EN_BITS(value)) || in sifive_pwm_write()
327 (HAS_PWM_EN_BITS(s->pwmcfg) && !HAS_PWM_EN_BITS(value))) { in sifive_pwm_write()
331 s->pwmcfg = value; in sifive_pwm_write()
335 new_offset = value; in sifive_pwm_write()
345 new_offset = (((value & PWMCMP_MASK) << scale) & PWMCOUNT_MASK); in sifive_pwm_write()
354 s->pwmcmp[0] = value & PWMCMP_MASK; in sifive_pwm_write()
357 s->pwmcmp[1] = value & PWMCMP_MASK; in sifive_pwm_write()
360 s->pwmcmp[2] = value & PWMCMP_MASK; in sifive_pwm_write()
363 s->pwmcmp[3] = value & PWMCMP_MASK; in sifive_pwm_write()