Lines Matching +full:no +full:- +full:read +full:- +full:rollover
8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
12 * the COPYING file in the top-level directory.
62 CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int()
71 qemu_irq_raise(s->irq); in imx_epit_update_int()
73 qemu_irq_lower(s->irq); in imx_epit_update_int()
79 uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); in imx_epit_get_freq()
80 uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); in imx_epit_get_freq()
81 uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]); in imx_epit_get_freq()
94 s->cr = 0; in imx_epit_reset()
96 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); in imx_epit_reset()
98 s->sr = 0; in imx_epit_reset()
99 s->lr = EPIT_TIMER_MAX; in imx_epit_reset()
100 s->cmp = 0; in imx_epit_reset()
101 ptimer_transaction_begin(s->timer_cmp); in imx_epit_reset()
102 ptimer_transaction_begin(s->timer_reload); in imx_epit_reset()
106 * set, the timers are no longer running. in imx_epit_reset()
109 ptimer_stop(s->timer_cmp); in imx_epit_reset()
110 ptimer_stop(s->timer_reload); in imx_epit_reset()
112 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); in imx_epit_reset()
113 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); in imx_epit_reset()
114 ptimer_transaction_commit(s->timer_cmp); in imx_epit_reset()
115 ptimer_transaction_commit(s->timer_reload); in imx_epit_reset()
125 reg_value = s->cr; in imx_epit_read()
129 reg_value = s->sr; in imx_epit_read()
132 case 2: /* LR - ticks*/ in imx_epit_read()
133 reg_value = s->lr; in imx_epit_read()
137 reg_value = s->cmp; in imx_epit_read()
141 reg_value = ptimer_get_count(s->timer_reload); in imx_epit_read()
157 * s->timer_cmp, but outside of a transaction block of s->timer_reload,
158 * so the proper counter value is read.
168 bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); in imx_epit_update_compare_timer()
173 * on it are committed here. Otherwise stale values are be read. in imx_epit_update_compare_timer()
175 counter = ptimer_get_count(s->timer_reload); in imx_epit_update_compare_timer()
176 uint64_t limit = ptimer_get_limit(s->timer_cmp); in imx_epit_update_compare_timer()
182 is_oneshot = (limit < s->cmp); in imx_epit_update_compare_timer()
183 if (counter >= s->cmp) { in imx_epit_update_compare_timer()
185 counter -= s->cmp; in imx_epit_update_compare_timer()
190 * value calculated below can be above the 32-bit limit, which in imx_epit_update_compare_timer()
194 counter += limit - s->cmp; in imx_epit_update_compare_timer()
208 * compare timer needs to run even if no interrupts are to be generated, in imx_epit_update_compare_timer()
216 ptimer_set_count(s->timer_cmp, counter); in imx_epit_update_compare_timer()
217 ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0); in imx_epit_update_compare_timer()
219 ptimer_stop(s->timer_cmp); in imx_epit_update_compare_timer()
226 uint32_t oldcr = s->cr; in imx_epit_write_cr()
228 s->cr = value & 0x03ffffff; in imx_epit_write_cr()
230 if (s->cr & CR_SWR) { in imx_epit_write_cr()
238 uint32_t toggled_cr_bits = oldcr ^ s->cr; in imx_epit_write_cr()
239 /* re-initialize the limits if CR.RLD has changed */ in imx_epit_write_cr()
242 bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN; in imx_epit_write_cr()
243 bool set_counter = is_switched_on && (s->cr & CR_ENMOD); in imx_epit_write_cr()
245 ptimer_transaction_begin(s->timer_cmp); in imx_epit_write_cr()
246 ptimer_transaction_begin(s->timer_reload); in imx_epit_write_cr()
249 ptimer_set_freq(s->timer_reload, freq); in imx_epit_write_cr()
250 ptimer_set_freq(s->timer_cmp, freq); in imx_epit_write_cr()
254 uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; in imx_epit_write_cr()
255 ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); in imx_epit_write_cr()
257 ptimer_set_limit(s->timer_cmp, limit, 0); in imx_epit_write_cr()
265 if (freq && (s->cr & CR_EN)) { in imx_epit_write_cr()
266 ptimer_run(s->timer_reload, 0); in imx_epit_write_cr()
268 ptimer_stop(s->timer_reload); in imx_epit_write_cr()
271 ptimer_transaction_commit(s->timer_reload); in imx_epit_write_cr()
274 ptimer_transaction_commit(s->timer_cmp); in imx_epit_write_cr()
279 * - reset clears both SR.OCIF and CR.OCIE in imx_epit_write_cr()
280 * - write to CR.EN or CR.OCIE in imx_epit_write_cr()
289 s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ in imx_epit_write_sr()
296 s->lr = value; in imx_epit_write_lr()
298 ptimer_transaction_begin(s->timer_cmp); in imx_epit_write_lr()
299 ptimer_transaction_begin(s->timer_reload); in imx_epit_write_lr()
300 if (s->cr & CR_RLD) { in imx_epit_write_lr()
303 ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); in imx_epit_write_lr()
304 ptimer_set_limit(s->timer_cmp, s->lr, 0); in imx_epit_write_lr()
305 } else if (s->cr & CR_IOVW) { in imx_epit_write_lr()
307 ptimer_set_count(s->timer_reload, s->lr); in imx_epit_write_lr()
309 /* Commit the changes to s->timer_reload, so they can propagate. */ in imx_epit_write_lr()
310 ptimer_transaction_commit(s->timer_reload); in imx_epit_write_lr()
313 ptimer_transaction_commit(s->timer_cmp); in imx_epit_write_lr()
318 s->cmp = value; in imx_epit_write_cmp()
321 ptimer_transaction_begin(s->timer_cmp); in imx_epit_write_cmp()
323 ptimer_transaction_commit(s->timer_cmp); in imx_epit_write_cmp()
363 assert(s->cr & CR_EN); in imx_epit_cmp()
365 DPRINTF("sr was %d\n", s->sr); in imx_epit_cmp()
367 s->sr |= SR_OCIF; in imx_epit_cmp()
373 /* No action required on rollover of timer_reload */ in imx_epit_reload()
377 .read = imx_epit_read,
404 sysbus_init_irq(sbd, &s->irq); in imx_epit_realize()
405 memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, in imx_epit_realize()
407 sysbus_init_mmio(sbd, &s->iomem); in imx_epit_realize()
415 s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); in imx_epit_realize()
421 s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); in imx_epit_realize()
434 dc->realize = imx_epit_realize; in imx_epit_class_init()
436 dc->vmsd = &vmstate_imx_timer_epit; in imx_epit_class_init()
437 dc->desc = "i.MX periodic timer"; in imx_epit_class_init()