Lines Matching +full:mode +full:- +full:xxx
4 * Copyright (c) 2003-2004 Fabrice Bellard
57 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, in pit_get_count()
59 switch(s->mode) { in pit_get_count()
64 counter = (s->count - d) & 0xffff; in pit_get_count()
67 /* XXX: may be incorrect for odd counts */ in pit_get_count()
68 counter = s->count - ((2 * d) % s->count); in pit_get_count()
71 counter = s->count - (d % s->count); in pit_get_count()
81 switch (sc->mode) { in pit_set_channel_gate()
85 /* XXX: just disable/enable counting */ in pit_set_channel_gate()
89 if (sc->gate < val) { in pit_set_channel_gate()
91 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in pit_set_channel_gate()
92 pit_irq_timer_update(sc, sc->count_load_time); in pit_set_channel_gate()
97 if (sc->gate < val) { in pit_set_channel_gate()
99 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in pit_set_channel_gate()
100 pit_irq_timer_update(sc, sc->count_load_time); in pit_set_channel_gate()
102 /* XXX: disable/enable counting */ in pit_set_channel_gate()
105 sc->gate = val; in pit_set_channel_gate()
112 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in pit_load_count()
113 s->count = val; in pit_load_count()
114 pit_irq_timer_update(s, s->count_load_time); in pit_load_count()
120 if (!s->count_latched) { in pit_latch_count()
121 s->latched_count = pit_get_count(s); in pit_latch_count()
122 s->count_latched = s->rw_mode; in pit_latch_count()
139 s = &pit->channels[channel]; in pit_ioport_write()
144 if (!(val & 0x10) && !s->status_latched) { in pit_ioport_write()
146 /* XXX: add BCD and null count */ in pit_ioport_write()
147 s->status = in pit_ioport_write()
150 (s->rw_mode << 4) | in pit_ioport_write()
151 (s->mode << 1) | in pit_ioport_write()
152 s->bcd; in pit_ioport_write()
153 s->status_latched = 1; in pit_ioport_write()
158 s = &pit->channels[channel]; in pit_ioport_write()
163 s->rw_mode = access; in pit_ioport_write()
164 s->read_state = access; in pit_ioport_write()
165 s->write_state = access; in pit_ioport_write()
167 s->mode = (val >> 1) & 7; in pit_ioport_write()
168 s->bcd = val & 1; in pit_ioport_write()
169 /* XXX: update irq timer ? */ in pit_ioport_write()
173 s = &pit->channels[addr]; in pit_ioport_write()
174 switch(s->write_state) { in pit_ioport_write()
183 s->write_latch = val; in pit_ioport_write()
184 s->write_state = RW_STATE_WORD1; in pit_ioport_write()
187 pit_load_count(s, s->write_latch | (val << 8)); in pit_ioport_write()
188 s->write_state = RW_STATE_WORD0; in pit_ioport_write()
204 /* Mode/Command register is write only, read is ignored */ in pit_ioport_read()
208 s = &pit->channels[addr]; in pit_ioport_read()
209 if (s->status_latched) { in pit_ioport_read()
210 s->status_latched = 0; in pit_ioport_read()
211 ret = s->status; in pit_ioport_read()
212 } else if (s->count_latched) { in pit_ioport_read()
213 switch(s->count_latched) { in pit_ioport_read()
216 ret = s->latched_count & 0xff; in pit_ioport_read()
217 s->count_latched = 0; in pit_ioport_read()
220 ret = s->latched_count >> 8; in pit_ioport_read()
221 s->count_latched = 0; in pit_ioport_read()
224 ret = s->latched_count & 0xff; in pit_ioport_read()
225 s->count_latched = RW_STATE_MSB; in pit_ioport_read()
229 switch(s->read_state) { in pit_ioport_read()
242 s->read_state = RW_STATE_WORD1; in pit_ioport_read()
247 s->read_state = RW_STATE_WORD0; in pit_ioport_read()
259 if (!s->irq_timer || s->irq_disabled) { in pit_irq_timer_update()
264 qemu_set_irq(s->irq, irq_level); in pit_irq_timer_update()
268 (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); in pit_irq_timer_update()
270 s->next_transition_time = expire_time; in pit_irq_timer_update()
271 if (expire_time != -1) in pit_irq_timer_update()
272 timer_mod(s->irq_timer, expire_time); in pit_irq_timer_update()
274 timer_del(s->irq_timer); in pit_irq_timer_update()
281 pit_irq_timer_update(s, s->next_transition_time); in pit_irq_timer()
291 s = &pit->channels[0]; in pit_reset()
292 if (!s->irq_disabled) { in pit_reset()
293 timer_mod(s->irq_timer, s->next_transition_time); in pit_reset()
297 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
298 * reenable it when legacy mode is left again. */
302 PITChannelState *s = &pit->channels[0]; in pit_irq_control()
305 s->irq_disabled = 0; in pit_irq_control()
308 s->irq_disabled = 1; in pit_irq_control()
309 timer_del(s->irq_timer); in pit_irq_control()
325 PITChannelState *sc = &s->channels[0]; in pit_post_load()
327 if (sc->next_transition_time != -1 && !sc->irq_disabled) { in pit_post_load()
328 timer_mod(sc->irq_timer, sc->next_transition_time); in pit_post_load()
330 timer_del(sc->irq_timer); in pit_post_load()
340 s = &pit->channels[0]; in pit_realizefn()
342 s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); in pit_realizefn()
343 qdev_init_gpio_out(dev, &s->irq, 1); in pit_realizefn()
345 memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, in pit_realizefn()
350 pc->parent_realize(dev, errp); in pit_realizefn()
359 device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize); in pit_class_initfn()
360 k->set_channel_gate = pit_set_channel_gate; in pit_class_initfn()
361 k->get_channel_info = pit_get_channel_info_common; in pit_class_initfn()
362 k->post_load = pit_post_load; in pit_class_initfn()