Lines Matching refs:timer
79 HPETTimer timer[HPET_MAX_TIMERS]; member
94 static uint32_t timer_int_route(struct HPETTimer *timer) in timer_int_route() argument
96 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; in timer_int_route()
184 static void update_irq(struct HPETTimer *timer, int set) in update_irq() argument
190 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { in update_irq()
195 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; in update_irq()
197 route = timer_int_route(timer); in update_irq()
199 s = timer->state; in update_irq()
200 mask = 1 << timer->tn; in update_irq()
202 if (set && (timer->config & HPET_TN_TYPE_LEVEL)) { in update_irq()
212 if (set && timer_enabled(timer) && hpet_enabled(s)) { in update_irq()
213 if (timer_fsb_route(timer)) { in update_irq()
214 address_space_stl_le(&address_space_memory, timer->fsb >> 32, in update_irq()
215 timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED, in update_irq()
217 } else if (timer->config & HPET_TN_TYPE_LEVEL) { in update_irq()
223 if (!timer_fsb_route(timer)) { in update_irq()
268 HPETTimer *t = &s->timer[i]; in hpet_post_load()
285 if (s->timer[0].config & HPET_TN_FSB_CAP) { in hpet_post_load()
356 VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
449 HPETTimer *timer = &s->timer[timer_id]; in hpet_ram_read() local
458 return timer->config >> shift; in hpet_ram_read()
460 return timer->cmp >> shift; in hpet_ram_read()
462 return timer->fsb >> shift; in hpet_ram_read()
505 HPETTimer *timer = &s->timer[timer_id]; in hpet_ram_write() local
515 old_val = timer->config; in hpet_ram_write()
523 update_irq(timer, 0); in hpet_ram_write()
525 timer->config = new_val; in hpet_ram_write()
528 update_irq(timer, 1); in hpet_ram_write()
531 timer->cmp = (uint32_t)timer->cmp; in hpet_ram_write()
532 timer->period = (uint32_t)timer->period; in hpet_ram_write()
535 hpet_set_timer(timer); in hpet_ram_write()
539 if (timer->config & HPET_TN_32BIT) { in hpet_ram_write()
549 if (!timer_is_periodic(timer) in hpet_ram_write()
550 || (timer->config & HPET_TN_SETVAL)) { in hpet_ram_write()
551 timer->cmp = deposit64(timer->cmp, shift, len, value); in hpet_ram_write()
553 if (timer_is_periodic(timer)) { in hpet_ram_write()
554 timer->period = deposit64(timer->period, shift, len, value); in hpet_ram_write()
556 timer->config &= ~HPET_TN_SETVAL; in hpet_ram_write()
558 hpet_set_timer(timer); in hpet_ram_write()
562 timer->fsb = deposit64(timer->fsb, shift, len, value); in hpet_ram_write()
583 if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) { in hpet_ram_write()
584 update_irq(&s->timer[i], 1); in hpet_ram_write()
586 hpet_set_timer(&s->timer[i]); in hpet_ram_write()
592 hpet_del_timer(&s->timer[i]); in hpet_ram_write()
612 update_irq(&s->timer[i], 0); in hpet_ram_write()
650 HPETTimer *timer = &s->timer[i]; in hpet_reset() local
652 hpet_del_timer(timer); in hpet_reset()
653 timer->cmp = ~0ULL; in hpet_reset()
654 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; in hpet_reset()
656 timer->config |= HPET_TN_FSB_CAP; in hpet_reset()
659 timer->config |= (uint64_t)s->intcap << 32; in hpet_reset()
660 timer->period = 0ULL; in hpet_reset()
661 timer->wrap_flag = 0; in hpet_reset()
706 HPETTimer *timer; in hpet_realize() local
733 timer = &s->timer[i]; in hpet_realize()
734 timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer); in hpet_realize()
735 timer->tn = i; in hpet_realize()
736 timer->state = s; in hpet_realize()