1066     uint32_t value = 0;  in exynos4210_mct_read()  local
1072         value = s->reg_mct_cfg;  in exynos4210_mct_read()
1078         value = UINT32_MAX & (count >> shift);  in exynos4210_mct_read()
1083         value = s->g_timer.reg.cnt_wstat;  in exynos4210_mct_read()
1090         value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);  in exynos4210_mct_read()
1094         value = s->g_timer.reg.tcon;  in exynos4210_mct_read()
1098         value = s->g_timer.reg.int_cstat;  in exynos4210_mct_read()
1102         value = s->g_timer.reg.int_enb;  in exynos4210_mct_read()
1105         value = s->g_timer.reg.wstat;  in exynos4210_mct_read()
1110         value = s->g_timer.reg.comp_add_incr[GET_G_COMP_ADD_INCR_IDX(offset)];  in exynos4210_mct_read()
1118         value = s->l_timer[lt_i].reg.cnt[index];  in exynos4210_mct_read()
1124         value = exynos4210_ltick_cnt_get_cnto(&s->l_timer[lt_i].tick_timer);  in exynos4210_mct_read()
1125         DPRINTF("local timer[%d] read TCNTO %x\n", lt_i, value);  in exynos4210_mct_read()
1131         value = exynos4210_ltick_int_get_cnto(&s->l_timer[lt_i].tick_timer);  in exynos4210_mct_read()
1132         DPRINTF("local timer[%d] read ICNTO %x\n", lt_i, value);  in exynos4210_mct_read()
1138         value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);  in exynos4210_mct_read()
1143         value = s->l_timer[lt_i].reg.tcon;  in exynos4210_mct_read()
1148         value = s->l_timer[lt_i].reg.int_cstat;  in exynos4210_mct_read()
1153         value = s->l_timer[lt_i].reg.int_enb;  in exynos4210_mct_read()
1158         value = s->l_timer[lt_i].reg.wstat;  in exynos4210_mct_read()
1166     return value;  in exynos4210_mct_read()
1171         uint64_t value, unsigned size)  in exynos4210_mct_write()  argument
1192         s->reg_mct_cfg = value;  in exynos4210_mct_write()
1200             DPRINTF("global timer write to reg.cntl %llx\n", value);  in exynos4210_mct_write()
1202             new_frc = (s->g_timer.reg.cnt & (uint64_t)UINT32_MAX << 32) + value;  in exynos4210_mct_write()
1207             DPRINTF("global timer write to reg.cntu %llx\n", value);  in exynos4210_mct_write()
1210                     ((uint64_t)value << 32);  in exynos4210_mct_write()
1221         s->g_timer.reg.cnt_wstat &= ~(value);  in exynos4210_mct_write()
1231                 (value << shift);  in exynos4210_mct_write()
1233         DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);  in exynos4210_mct_write()
1248         s->g_timer.reg.tcon = value;  in exynos4210_mct_write()
1251         DPRINTF("global timer write to reg.g_tcon %llx\n", value);  in exynos4210_mct_write()
1256         if ((value & G_TCON_TIMER_ENABLE) > (old_val &  in exynos4210_mct_write()
1260         if ((value & G_TCON_TIMER_ENABLE) < (old_val &  in exynos4210_mct_write()
1267             if ((value & G_TCON_COMP_ENABLE(i)) != (old_val &  in exynos4210_mct_write()
1277         s->g_timer.reg.int_cstat &= ~(value);  in exynos4210_mct_write()
1279             if (value & G_INT_CSTAT_COMP(i)) {  in exynos4210_mct_write()
1288             if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &  in exynos4210_mct_write()
1295             if ((value & G_INT_ENABLE(i)) < (s->g_timer.reg.tcon &  in exynos4210_mct_write()
1301         DPRINTF("global timer INT enable %llx\n", value);  in exynos4210_mct_write()
1302         s->g_timer.reg.int_enb = value;  in exynos4210_mct_write()
1306         s->g_timer.reg.wstat &= ~(value);  in exynos4210_mct_write()
1312         s->g_timer.reg.comp_add_incr[index] = value;  in exynos4210_mct_write()
1322         s->l_timer[lt_i].reg.tcon = value;  in exynos4210_mct_write()
1326         if ((value & L_TCON_TICK_START) <  in exynos4210_mct_write()
1333         if ((value & L_TCON_INT_START) <  in exynos4210_mct_write()
1340         if ((value & L_TCON_TICK_START) >  in exynos4210_mct_write()
1347         if ((value & L_TCON_INT_START) >  in exynos4210_mct_write()
1356         if ((value & L_TCON_FRC_START) >  in exynos4210_mct_write()
1361         if ((value & L_TCON_FRC_START) <  in exynos4210_mct_write()
1378         exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value,  in exynos4210_mct_write()
1383         s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value;  in exynos4210_mct_write()
1386         if (tcntb_min[lt_i] > value) {  in exynos4210_mct_write()
1387             tcntb_min[lt_i] = value;  in exynos4210_mct_write()
1389         if (tcntb_max[lt_i] < value) {  in exynos4210_mct_write()
1390             tcntb_max[lt_i] = value;  in exynos4210_mct_write()
1393                 lt_i, value, tcntb_max[lt_i], tcntb_min[lt_i]);  in exynos4210_mct_write()
1401         s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = value &  in exynos4210_mct_write()
1420         if (value & L_ICNTB_MANUAL_UPDATE) {  in exynos4210_mct_write()
1427         if (icntb_min[lt_i] > value) {  in exynos4210_mct_write()
1428             icntb_min[lt_i] = value;  in exynos4210_mct_write()
1430         if (icntb_max[lt_i] < value) {  in exynos4210_mct_write()
1431             icntb_max[lt_i] = value;  in exynos4210_mct_write()
1434                 lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);  in exynos4210_mct_write()
1440         DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i, value);  in exynos4210_mct_write()
1443         s->l_timer[lt_i].reg.cnt[L_REG_CNT_FRCCNTB] = value;  in exynos4210_mct_write()
1458         DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i, value);  in exynos4210_mct_write()
1460         s->l_timer[lt_i].reg.int_cstat &= ~value;  in exynos4210_mct_write()
1471         if ((value & L_INT_INTENB_ICNTEIE) > (old_val & L_INT_INTENB_ICNTEIE)) {  in exynos4210_mct_write()
1477         s->l_timer[lt_i].reg.int_enb = value;  in exynos4210_mct_write()
1484         s->l_timer[lt_i].reg.wstat &= ~value;  in exynos4210_mct_write()