Lines Matching +full:break +full:- +full:control
20 #include "hw/qdev-properties.h"
22 #include "hw/timer/allwinner-a10-pit.h"
32 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); in a10_pit_update_irq()
43 return s->irq_enable; in a10_pit_read()
45 return s->irq_status; in a10_pit_read()
49 index -= 1; in a10_pit_read()
52 return s->control[index]; in a10_pit_read()
54 return s->interval[index]; in a10_pit_read()
56 s->count[index] = ptimer_get_count(s->timer[index]); in a10_pit_read()
57 return s->count[index]; in a10_pit_read()
61 break; in a10_pit_read()
64 break; in a10_pit_read()
66 break; in a10_pit_read()
68 return s->count_lo; in a10_pit_read()
70 return s->count_hi; in a10_pit_read()
72 return s->count_ctl; in a10_pit_read()
76 break; in a10_pit_read()
82 /* Must be called inside a ptimer transaction block for s->timer[index] */
87 prescaler = 1 << extract32(s->control[index], 4, 3); in a10_pit_set_freq()
88 source = extract32(s->control[index], 2, 2); in a10_pit_set_freq()
89 source_freq = s->clk_freq[source]; in a10_pit_set_freq()
92 ptimer_set_freq(s->timer[index], source_freq / prescaler); in a10_pit_set_freq()
107 s->irq_enable = value; in a10_pit_write()
109 break; in a10_pit_write()
111 s->irq_status &= ~value; in a10_pit_write()
113 break; in a10_pit_write()
117 index -= 1; in a10_pit_write()
120 s->control[index] = value; in a10_pit_write()
121 ptimer_transaction_begin(s->timer[index]); in a10_pit_write()
123 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { in a10_pit_write()
124 ptimer_set_count(s->timer[index], s->interval[index]); in a10_pit_write()
126 if (s->control[index] & AW_A10_PIT_TIMER_EN) { in a10_pit_write()
128 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { in a10_pit_write()
131 ptimer_run(s->timer[index], oneshot); in a10_pit_write()
133 ptimer_stop(s->timer[index]); in a10_pit_write()
135 ptimer_transaction_commit(s->timer[index]); in a10_pit_write()
136 break; in a10_pit_write()
138 s->interval[index] = value; in a10_pit_write()
139 ptimer_transaction_begin(s->timer[index]); in a10_pit_write()
140 ptimer_set_limit(s->timer[index], s->interval[index], 1); in a10_pit_write()
141 ptimer_transaction_commit(s->timer[index]); in a10_pit_write()
142 break; in a10_pit_write()
144 s->count[index] = value; in a10_pit_write()
145 break; in a10_pit_write()
150 break; in a10_pit_write()
152 s->watch_dog_control = value; in a10_pit_write()
153 break; in a10_pit_write()
155 s->watch_dog_mode = value; in a10_pit_write()
156 break; in a10_pit_write()
158 s->count_lo = value; in a10_pit_write()
159 break; in a10_pit_write()
161 s->count_hi = value; in a10_pit_write()
162 break; in a10_pit_write()
164 s->count_ctl = value; in a10_pit_write()
165 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { in a10_pit_write()
168 s->count_lo = tmp_count; in a10_pit_write()
169 s->count_hi = tmp_count >> 32; in a10_pit_write()
170 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; in a10_pit_write()
172 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { in a10_pit_write()
173 s->count_lo = 0; in a10_pit_write()
174 s->count_hi = 0; in a10_pit_write()
175 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; in a10_pit_write()
177 break; in a10_pit_write()
181 break; in a10_pit_write()
192 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
193 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
194 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
195 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
205 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
223 s->irq_enable = 0; in a10_pit_reset()
224 s->irq_status = 0; in a10_pit_reset()
228 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; in a10_pit_reset()
229 s->interval[i] = 0; in a10_pit_reset()
230 s->count[i] = 0; in a10_pit_reset()
231 ptimer_transaction_begin(s->timer[i]); in a10_pit_reset()
232 ptimer_stop(s->timer[i]); in a10_pit_reset()
234 ptimer_transaction_commit(s->timer[i]); in a10_pit_reset()
236 s->watch_dog_mode = 0; in a10_pit_reset()
237 s->watch_dog_control = 0; in a10_pit_reset()
238 s->count_lo = 0; in a10_pit_reset()
239 s->count_hi = 0; in a10_pit_reset()
240 s->count_ctl = 0; in a10_pit_reset()
246 AwA10PITState *s = tc->container; in a10_pit_timer_cb()
247 uint8_t i = tc->index; in a10_pit_timer_cb()
249 if (s->control[i] & AW_A10_PIT_TIMER_EN) { in a10_pit_timer_cb()
250 s->irq_status |= 1 << i; in a10_pit_timer_cb()
251 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { in a10_pit_timer_cb()
252 ptimer_stop(s->timer[i]); in a10_pit_timer_cb()
253 s->control[i] &= ~AW_A10_PIT_TIMER_EN; in a10_pit_timer_cb()
266 sysbus_init_irq(sbd, &s->irq[i]); in a10_pit_init()
268 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, in a10_pit_init()
270 sysbus_init_mmio(sbd, &s->iomem); in a10_pit_init()
273 AwA10TimerContext *tc = &s->timer_context[i]; in a10_pit_init()
275 tc->container = s; in a10_pit_init()
276 tc->index = i; in a10_pit_init()
277 s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_LEGACY); in a10_pit_init()
287 ptimer_free(s->timer[i]); in a10_pit_finalize()
297 dc->desc = "allwinner a10 timer"; in a10_pit_class_init()
298 dc->vmsd = &vmstate_a10_pit; in a10_pit_class_init()