34 #include "hw/qdev-properties.h"
51 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
52 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
53 #define IRQ_DRR_FULL         (1 << (31 - 27))
56 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
80 #define TYPE_XILINX_SPI "xlnx.xps-spi"
104     fifo8_reset(&s->tx_fifo);  in txfifo_reset()
106     s->regs[R_SPISR] &= ~SR_TX_FULL;  in txfifo_reset()
107     s->regs[R_SPISR] |= SR_TX_EMPTY;  in txfifo_reset()
112     fifo8_reset(&s->rx_fifo);  in rxfifo_reset()
114     s->regs[R_SPISR] |= SR_RX_EMPTY;  in rxfifo_reset()
115     s->regs[R_SPISR] &= ~SR_RX_FULL;  in rxfifo_reset()
122     for (i = 0; i < s->num_cs; ++i) {  in xlx_spi_update_cs()
123         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));  in xlx_spi_update_cs()
131     s->regs[R_IPISR] |=  in xlx_spi_update_irq()
132             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |  in xlx_spi_update_irq()
133             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);  in xlx_spi_update_irq()
135     pending = s->regs[R_IPISR] & s->regs[R_IPIER];  in xlx_spi_update_irq()
137     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);  in xlx_spi_update_irq()
142     if (pending != s->irqline) {  in xlx_spi_update_irq()
143         s->irqline = pending;  in xlx_spi_update_irq()
145                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);  in xlx_spi_update_irq()
146         qemu_set_irq(s->irq, pending);  in xlx_spi_update_irq()
153     memset(s->regs, 0, sizeof s->regs);  in xlx_spi_do_reset()
158     s->regs[R_SPISSR] = ~0;  in xlx_spi_do_reset()
159     s->regs[R_SPICR] = R_SPICR_MTI;  in xlx_spi_do_reset()
171     return !(s->regs[R_SPICR] & R_SPICR_MTI);  in spi_master_enabled()
179     while (!fifo8_is_empty(&s->tx_fifo)) {  in spi_flush_txfifo()
180         tx = (uint32_t)fifo8_pop(&s->tx_fifo);  in spi_flush_txfifo()
182         rx = ssi_transfer(s->spi, tx);  in spi_flush_txfifo()
184         if (fifo8_is_full(&s->rx_fifo)) {  in spi_flush_txfifo()
185             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;  in spi_flush_txfifo()
187             fifo8_push(&s->rx_fifo, (uint8_t)rx);  in spi_flush_txfifo()
188             if (fifo8_is_full(&s->rx_fifo)) {  in spi_flush_txfifo()
189                 s->regs[R_SPISR] |= SR_RX_FULL;  in spi_flush_txfifo()
190                 s->regs[R_IPISR] |= IRQ_DRR_FULL;  in spi_flush_txfifo()
194         s->regs[R_SPISR] &= ~SR_RX_EMPTY;  in spi_flush_txfifo()
195         s->regs[R_SPISR] &= ~SR_TX_FULL;  in spi_flush_txfifo()
196         s->regs[R_SPISR] |= SR_TX_EMPTY;  in spi_flush_txfifo()
198         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;  in spi_flush_txfifo()
199         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;  in spi_flush_txfifo()
213         if (fifo8_is_empty(&s->rx_fifo)) {  in spi_read()
218         s->regs[R_SPISR] &= ~SR_RX_FULL;  in spi_read()
219         r = fifo8_pop(&s->rx_fifo);  in spi_read()
220         if (fifo8_is_empty(&s->rx_fifo)) {  in spi_read()
221             s->regs[R_SPISR] |= SR_RX_EMPTY;  in spi_read()
226         r = s->regs[addr];  in spi_read()
230         if (addr < ARRAY_SIZE(s->regs)) {  in spi_read()
231             r = s->regs[addr];  in spi_read()
260         s->regs[R_SPISR] &= ~SR_TX_EMPTY;  in spi_write()
261         fifo8_push(&s->tx_fifo, (uint8_t)value);  in spi_write()
262         if (fifo8_is_full(&s->tx_fifo)) {  in spi_write()
263             s->regs[R_SPISR] |= SR_TX_FULL;  in spi_write()
278         /* Toggle the bits.  */  in spi_write()
279         s->regs[addr] ^= value;  in spi_write()
284         s->regs[addr] = value;  in spi_write()
298         s->regs[addr] = value;  in spi_write()
306         if (addr < ARRAY_SIZE(s->regs)) {  in spi_write()
307             s->regs[addr] = value;  in spi_write()
334     s->spi = ssi_create_bus(dev, "spi");  in xilinx_spi_realize()
336     sysbus_init_irq(sbd, &s->irq);  in xilinx_spi_realize()
337     s->cs_lines = g_new0(qemu_irq, s->num_cs);  in xilinx_spi_realize()
338     for (i = 0; i < s->num_cs; ++i) {  in xilinx_spi_realize()
339         sysbus_init_irq(sbd, &s->cs_lines[i]);  in xilinx_spi_realize()
342     memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,  in xilinx_spi_realize()
343                           "xilinx-spi", R_MAX * 4);  in xilinx_spi_realize()
344     sysbus_init_mmio(sbd, &s->mmio);  in xilinx_spi_realize()
346     s->irqline = -1;  in xilinx_spi_realize()
348     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);  in xilinx_spi_realize()
349     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);  in xilinx_spi_realize()
365     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
373     dc->realize = xilinx_spi_realize;  in xilinx_spi_class_init()
376     dc->vmsd = &vmstate_xilinx_spi;  in xilinx_spi_class_init()