347     uint32_t val32 = val64;  in ibex_spi_host_write()  local
360         if (FIELD_EX32(val32, INTR_STATE, ERROR)) {  in ibex_spi_host_write()
363         if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {  in ibex_spi_host_write()
369         s->regs[addr] = val32;  in ibex_spi_host_write()
372         s->regs[addr] = val32;  in ibex_spi_host_write()
376         s->regs[addr] = val32;  in ibex_spi_host_write()
381         s->regs[addr] = val32;  in ibex_spi_host_write()
383         if (val32 & R_CONTROL_SW_RST_MASK)  {  in ibex_spi_host_write()
389         if (val32 & R_CONTROL_OUTPUT_EN_MASK)  {  in ibex_spi_host_write()
396         s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32;  in ibex_spi_host_write()
402         if (val32 >= s->num_cs) {  in ibex_spi_host_write()
409         s->regs[addr] = val32;  in ibex_spi_host_write()
412         s->regs[addr] = val32;  in ibex_spi_host_write()
431         if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) {  in ibex_spi_host_write()
436         if (val32 & R_COMMAND_CSAAT_MASK)  {  in ibex_spi_host_write()
440         if (val32 & R_COMMAND_SPEED_MASK)  {  in ibex_spi_host_write()
482             fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));  in ibex_spi_host_write()
498         s->regs[addr] = val32;  in ibex_spi_host_write()
500         if (val32 & R_ERROR_ENABLE_CMDINVAL_MASK)  {  in ibex_spi_host_write()
513         if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {  in ibex_spi_host_write()
516         if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {  in ibex_spi_host_write()
519         if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {  in ibex_spi_host_write()
522         if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {  in ibex_spi_host_write()
525         if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {  in ibex_spi_host_write()
528         if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {  in ibex_spi_host_write()
535         s->regs[addr] = val32;  in ibex_spi_host_write()
537         if (val32 & R_EVENT_ENABLE_RXWM_MASK)  {  in ibex_spi_host_write()
541         if (val32 & R_EVENT_ENABLE_TXWM_MASK)  {  in ibex_spi_host_write()
546         if (val32 & R_EVENT_ENABLE_IDLE_MASK)  {  in ibex_spi_host_write()