35 #define SPI_INT_STA_REG  0x10 /* interrupt status register */  macro
149     case SPI_INT_STA_REG:  in allwinner_a10_spi_get_regname()
176     s->regs[REG_INDEX(SPI_INT_STA_REG)] |= (SPI_INT_STA_TE | SPI_INT_STA_TE14 |  in allwinner_a10_spi_txfifo_reset()
178     s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~(SPI_INT_STA_TU | SPI_INT_STA_TO);  in allwinner_a10_spi_txfifo_reset()
184     s->regs[REG_INDEX(SPI_INT_STA_REG)] &=  in allwinner_a10_spi_rxfifo_reset()
202     s->regs[REG_INDEX(SPI_INT_STA_REG)] = SPI_INT_STA_RESET;  in allwinner_a10_spi_reset_hold()
219         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RR;  in allwinner_a10_spi_update_irq()
221         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RR;  in allwinner_a10_spi_update_irq()
225         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF14;  in allwinner_a10_spi_update_irq()
227         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF14;  in allwinner_a10_spi_update_irq()
231         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RHF;  in allwinner_a10_spi_update_irq()
233         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RHF;  in allwinner_a10_spi_update_irq()
237         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF34;  in allwinner_a10_spi_update_irq()
239         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF34;  in allwinner_a10_spi_update_irq()
243         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF;  in allwinner_a10_spi_update_irq()
245         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_RF;  in allwinner_a10_spi_update_irq()
249         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE;  in allwinner_a10_spi_update_irq()
251         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE;  in allwinner_a10_spi_update_irq()
255         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE14;  in allwinner_a10_spi_update_irq()
257         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE14;  in allwinner_a10_spi_update_irq()
261         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_THE;  in allwinner_a10_spi_update_irq()
263         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_THE;  in allwinner_a10_spi_update_irq()
267         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TE34;  in allwinner_a10_spi_update_irq()
269         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TE34;  in allwinner_a10_spi_update_irq()
273         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TF;  in allwinner_a10_spi_update_irq()
275         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~SPI_INT_STA_TF;  in allwinner_a10_spi_update_irq()
278     level = (s->regs[REG_INDEX(SPI_INT_STA_REG)] &  in allwinner_a10_spi_update_irq()
318                 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_RF;  in allwinner_a10_spi_flush_txfifo()
329             s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TC;  in allwinner_a10_spi_flush_txfifo()
336         s->regs[REG_INDEX(SPI_INT_STA_REG)] |= SPI_INT_STA_TC;  in allwinner_a10_spi_flush_txfifo()
385         case SPI_INT_STA_REG:  in allwinner_a10_spi_read()
454     case SPI_INT_STA_REG:  in allwinner_a10_spi_write()
457         s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~(value & SPI_INT_STA_MASK);  in allwinner_a10_spi_write()