Lines Matching +full:bypass +full:- +full:slot +full:- +full:no
4 * Copyright (c) 2003-2005 Fabrice Bellard
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 #include "hw/qdev-properties.h"
32 #include "exec/address-spaces.h"
39 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
47 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
52 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
53 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
54 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
91 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
92 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
93 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
94 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
95 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
96 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
99 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
100 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
101 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
102 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
103 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
104 bypass enabled */
107 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
132 #define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
144 ret = s->regs[saddr]; in iommu_mem_read()
148 ret = s->regs[saddr]; in iommu_mem_read()
149 qemu_irq_lower(s->irq); in iommu_mem_read()
168 s->iostart = 0xffffffffff000000ULL; in iommu_mem_write()
171 s->iostart = 0xfffffffffe000000ULL; in iommu_mem_write()
174 s->iostart = 0xfffffffffc000000ULL; in iommu_mem_write()
177 s->iostart = 0xfffffffff8000000ULL; in iommu_mem_write()
180 s->iostart = 0xfffffffff0000000ULL; in iommu_mem_write()
183 s->iostart = 0xffffffffe0000000ULL; in iommu_mem_write()
186 s->iostart = 0xffffffffc0000000ULL; in iommu_mem_write()
190 s->iostart = 0xffffffff80000000ULL; in iommu_mem_write()
193 trace_sun4m_iommu_mem_writel_ctrl(s->iostart); in iommu_mem_write()
194 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); in iommu_mem_write()
197 s->regs[saddr] = val & IOMMU_BASE_MASK; in iommu_mem_write()
201 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; in iommu_mem_write()
205 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; in iommu_mem_write()
208 s->regs[saddr] = val; in iommu_mem_write()
209 qemu_irq_lower(s->irq); in iommu_mem_write()
212 s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; in iommu_mem_write()
215 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; in iommu_mem_write()
216 qemu_irq_lower(s->irq); in iommu_mem_write()
222 s->regs[saddr] = val & IOMMU_SBCFG_MASK; in iommu_mem_write()
227 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; in iommu_mem_write()
230 s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; in iommu_mem_write()
233 s->regs[saddr] = val; in iommu_mem_write()
254 iopte = s->regs[IOMMU_BASE] << 4; in iommu_page_get_flags()
255 addr &= ~s->iostart; in iommu_page_get_flags()
256 iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; in iommu_page_get_flags()
277 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | in iommu_bad_addr()
280 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; in iommu_bad_addr()
282 s->regs[IOMMU_AFAR] = addr; in iommu_bad_addr()
283 qemu_irq_raise(s->irq); in iommu_bad_addr()
345 memset(s->regs, 0, IOMMU_NREGS * 4); in iommu_reset()
346 s->iostart = 0; in iommu_reset()
347 s->regs[IOMMU_CTRL] = s->version; in iommu_reset()
348 s->regs[IOMMU_ARBEN] = IOMMU_MID; in iommu_reset()
349 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; in iommu_reset()
350 s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; in iommu_reset()
351 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; in iommu_reset()
359 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), in iommu_init()
361 "iommu-sun4m", UINT64_MAX); in iommu_init()
362 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); in iommu_init()
364 sysbus_init_irq(dev, &s->irq); in iommu_init()
366 memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", in iommu_init()
368 sysbus_init_mmio(dev, &s->iomem); in iommu_init()
381 dc->vmsd = &vmstate_iommu; in iommu_class_init()
397 imrc->translate = sun4m_translate_iommu; in sun4m_iommu_memory_region_class_init()