Lines Matching full:area
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
98 /* 0 - use area 5 wait states */
99 /* 1 - use area 6 wait states */
159 #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
160 #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */
552 #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
561 #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: */
562 /* 0 - Area 1 SRAM is set to */
564 /* 1 - Area 1 SRAM is set to byte */
566 #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: */
567 /* 0 - Area 4 SRAM is set to */
569 /* 1 - Area 4 SRAM is set to byte */
579 #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: */
597 #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */
598 #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */
599 #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM */
601 #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM */
603 #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM */
605 #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM */
608 #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */
609 #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */
610 #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM */
612 #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM */
614 #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM */
616 #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM */
619 #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */
620 #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */
621 #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM */
623 #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM */
625 #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM */
627 #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM */
630 #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */
631 #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or */
633 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 */
635 #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are */
637 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 */
639 #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM */
642 #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: */
651 #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */
653 #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */
655 #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */
657 #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */
659 #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */
661 #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */
663 #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */
680 #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
682 #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
684 #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
686 #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
688 #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
690 #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
692 #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
700 #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */
702 #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */
704 #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */
706 #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */
708 #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */
710 #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */
712 #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */
714 #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */
716 #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */
718 #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */
739 /* DRAM CAS\ Assertion Delay (area 3,2) */
761 #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */
762 #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */
764 #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */
765 #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */
767 #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */
768 #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */
770 #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */
771 #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */
773 #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */
774 #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */
776 #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */
777 #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */
779 #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */
780 #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */
900 #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait */
909 #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait */
918 #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Addr-OE\/WE\ Assertion Delay */
923 #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Addr-OE\/WE\ Assertion Delay */
935 #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Addr delay, */
941 #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay */