Lines Matching refs:MAX34451_NUM_PWR_DEVICES
46 #define MAX34451_NUM_PWR_DEVICES 16 macro
140 uint16_t power_good_on[MAX34451_NUM_PWR_DEVICES];
141 uint16_t power_good_off[MAX34451_NUM_PWR_DEVICES];
145 uint8_t status_mfr_specific[MAX34451_NUM_PWR_DEVICES];
152 uint16_t vout_peak[MAX34451_NUM_PWR_DEVICES];
153 uint16_t iout_peak[MAX34451_NUM_PWR_DEVICES];
155 uint16_t vout_min[MAX34451_NUM_PWR_DEVICES];
157 uint32_t fault_response[MAX34451_NUM_PWR_DEVICES];
163 uint16_t iout_avg[MAX34451_NUM_PWR_DEVICES];
164 uint16_t channel_config[MAX34451_NUM_PWR_DEVICES];
180 for (int i = 0; i < MAX34451_NUM_PWR_DEVICES; i++) { in max34451_check_limits()
421 if (pmdev->page < MAX34451_NUM_PWR_DEVICES) { in max34451_write_data()
427 if (pmdev->page < MAX34451_NUM_PWR_DEVICES) { in max34451_write_data()
624 for (int i = 0; i < MAX34451_NUM_PWR_DEVICES; i++) { in max34451_exit_reset()
645 MAX34451_NUM_PWR_DEVICES); in max34451_exit_reset()
646 memset_word(s->vout_min, DEFAULT_VMIN, MAX34451_NUM_PWR_DEVICES); in max34451_exit_reset()
660 MAX34451_NUM_PWR_DEVICES),
662 MAX34451_NUM_PWR_DEVICES),
670 MAX34451_NUM_PWR_DEVICES),
678 MAX34451_NUM_PWR_DEVICES),
680 MAX34451_NUM_PWR_DEVICES),
683 VMSTATE_UINT16_ARRAY(vout_min, MAX34451State, MAX34451_NUM_PWR_DEVICES),
686 MAX34451_NUM_PWR_DEVICES),
693 VMSTATE_UINT16_ARRAY(iout_avg, MAX34451State, MAX34451_NUM_PWR_DEVICES),
695 MAX34451_NUM_PWR_DEVICES),
716 for (int i = 0; i < MAX34451_NUM_PWR_DEVICES; i++) { in max34451_init()
729 for (int i = 0; i < MAX34451_NUM_PWR_DEVICES; i++) { in max34451_init()