Lines Matching full:since

46 #define SDHC_TRNS_ACMD23               0x0008 /* since v3 */
98 #define SDHC_CTRL_ADMA1_32             0x08 /* NOT ALLOWED since v2 */
194 /* Host Control Register 2 (since v3) */
201 FIELD(SDHC_HOSTCTL2, UHS_II_ENA,       8, 1); /* since v4 */
202 FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH,    10, 1); /* since v4 */
203 FIELD(SDHC_HOSTCTL2, CMD23_ENA,       11, 1); /* since v4 */
204 FIELD(SDHC_HOSTCTL2, VERSION4,        12, 1); /* since v4 */
214 FIELD(SDHC_CAPAB, EMBEDDED_8BIT,      18, 1); /* since v3 */
215 FIELD(SDHC_CAPAB, ADMA2,              19, 1); /* since v2 */
223 FIELD(SDHC_CAPAB, BUS64BIT_V4,        27, 1); /* since v4.10 */
224 FIELD(SDHC_CAPAB, BUS64BIT,           28, 1); /* since v2 */
225 FIELD(SDHC_CAPAB, ASYNC_INT,          29, 1); /* since v3 */
226 FIELD(SDHC_CAPAB, SLOT_TYPE,          30, 2); /* since v3 */
227 FIELD(SDHC_CAPAB, BUS_SPEED,          32, 3); /* since v3 */
228 FIELD(SDHC_CAPAB, UHS_II,             35, 8); /* since v4.20 */
229 FIELD(SDHC_CAPAB, DRIVER_STRENGTH,    36, 3); /* since v3 */
230 FIELD(SDHC_CAPAB, DRIVER_TYPE_A,      36, 1); /* since v3 */
231 FIELD(SDHC_CAPAB, DRIVER_TYPE_C,      37, 1); /* since v3 */
232 FIELD(SDHC_CAPAB, DRIVER_TYPE_D,      38, 1); /* since v3 */
233 FIELD(SDHC_CAPAB, TIMER_RETUNING,     40, 4); /* since v3 */
234 FIELD(SDHC_CAPAB, SDR50_TUNING,       45, 1); /* since v3 */
235 FIELD(SDHC_CAPAB, RETUNING_MODE,      46, 2); /* since v3 */
236 FIELD(SDHC_CAPAB, CLOCK_MULT,         48, 8); /* since v3 */
237 FIELD(SDHC_CAPAB, ADMA3,              59, 1); /* since v4.20 */
238 FIELD(SDHC_CAPAB, V18_VDD2,           60, 1); /* since v4.20 */
245 FIELD(SDHC_MAXCURR, V18_VDD2,         32, 8); /* since v4.20 */