Lines Matching +full:isa +full:- +full:base
4 * RISC-V virt ACPI generation
6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc
27 #include "hw/acpi/acpi-defs.h"
29 #include "hw/acpi/aml-build.h"
34 #include "hw/pci-host/gpex.h"
37 #include "hw/virtio/virtio-acpi.h"
40 #include "qemu/error-report.h"
69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); in riscv_acpi_madt_add_rintc()
70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; in riscv_acpi_madt_add_rintc()
75 socket_id = arch_ids->cpus[uid].props.node_id; in riscv_acpi_madt_add_rintc()
76 local_cpu_id = (arch_ids->cpus[uid].arch_id - in riscv_acpi_madt_add_rintc()
79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + in riscv_acpi_madt_add_rintc()
91 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { in riscv_acpi_madt_add_rintc()
94 arch_ids->cpus[uid].props.node_id, in riscv_acpi_madt_add_rintc()
97 } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { in riscv_acpi_madt_add_rintc()
100 arch_ids->cpus[uid].props.node_id, in riscv_acpi_madt_add_rintc()
107 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { in riscv_acpi_madt_add_rintc()
108 /* IMSIC Base address */ in riscv_acpi_madt_add_rintc()
122 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); in acpi_dsdt_add_cpus()
124 for (int i = 0; i < arch_ids->len; i++) { in acpi_dsdt_add_cpus()
131 aml_int(arch_ids->cpus[i].arch_id))); in acpi_dsdt_add_cpus()
136 aml_buffer(madt_buf->len, in acpi_dsdt_add_cpus()
137 (uint8_t *)madt_buf->data))); in acpi_dsdt_add_cpus()
177 aml_append(crs, aml_memory32_fixed(uart_memmap->base, in acpi_dsdt_add_uart()
178 uart_memmap->size, AML_READ_WRITE)); in acpi_dsdt_add_uart()
185 aml_append(pkg, aml_string("clock-frequency")); in acpi_dsdt_add_uart()
188 Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); in acpi_dsdt_add_uart()
215 .base_addr.addr = s->memmap[VIRT_UART0].base, in spcr_setup()
216 .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ in spcr_setup()
234 build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); in spcr_setup()
242 * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
243 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
244 * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
253 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); in build_rhct()
256 RISCVCPU *cpu = &s->soc[0].harts[0]; in build_rhct()
259 g_autofree char *isa = NULL; in build_rhct() local
261 AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, in build_rhct()
262 .oem_table_id = s->oem_table_id }; in build_rhct()
268 /* Time Base Frequency */ in build_rhct()
272 /* ISA + N hart info */ in build_rhct()
273 num_rhct_nodes = 1 + ms->smp.cpus; in build_rhct()
274 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { in build_rhct()
278 if (cpu->cfg.satp_mode.supported != 0) { in build_rhct()
288 /* ISA String Node */ in build_rhct()
289 isa_offset = table_data->len - table.table_offset; in build_rhct()
292 isa = riscv_isa_string(cpu); in build_rhct()
293 len = 8 + strlen(isa) + 1; in build_rhct()
299 /* ISA string length including NUL */ in build_rhct()
300 build_append_int_noprefix(table_data, strlen(isa) + 1, 2); in build_rhct()
301 g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */ in build_rhct()
308 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { in build_rhct()
309 cmo_offset = table_data->len - table.table_offset; in build_rhct()
316 if (cpu->cfg.cbom_blocksize) { in build_rhct()
318 __builtin_ctz(cpu->cfg.cbom_blocksize), in build_rhct()
328 if (cpu->cfg.cboz_blocksize) { in build_rhct()
330 __builtin_ctz(cpu->cfg.cboz_blocksize), in build_rhct()
338 if (cpu->cfg.satp_mode.supported != 0) { in build_rhct()
339 satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); in build_rhct()
340 mmu_offset = table_data->len - table.table_offset; in build_rhct()
358 for (int i = 0; i < arch_ids->len; i++) { in build_rhct()
406 build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id); in build_fadt_rev6()
417 const MemMapEntry *memmap = s->memmap; in build_dsdt()
418 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, in build_dsdt()
419 .oem_table_id = s->oem_table_id }; in build_dsdt()
438 if (s->aia_type == VIRT_AIA_TYPE_NONE) { in build_dsdt()
439 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base, in build_dsdt()
442 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base, in build_dsdt()
449 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, in build_dsdt()
454 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, in build_dsdt()
460 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, in build_dsdt()
470 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); in build_dsdt()
479 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
480 * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
481 * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
489 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); in build_madt()
491 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); in build_madt()
499 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { in build_madt()
500 imsic_max_hart_per_socket = s->soc[socket].num_harts; in build_madt()
506 AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, in build_madt()
507 .oem_table_id = s->oem_table_id }; in build_madt()
514 /* RISC-V Local INTC structures per HART */ in build_madt()
515 for (int i = 0; i < arch_ids->len; i++) { in build_madt()
520 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { in build_madt()
541 if (s->aia_type != VIRT_AIA_TYPE_NONE) { in build_madt()
544 aplic_addr = s->memmap[VIRT_APLIC_S].base + in build_madt()
545 s->memmap[VIRT_APLIC_S].size * socket; in build_madt()
554 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { in build_madt()
556 s->soc[socket].num_harts, in build_madt()
563 /* Global System Interrupt Base */ in build_madt()
569 s->memmap[VIRT_APLIC_S].size, 4); in build_madt()
574 aplic_addr = s->memmap[VIRT_PLIC].base + in build_madt()
575 s->memmap[VIRT_PLIC].size * socket; in build_madt()
584 VIRT_IRQCHIP_NUM_SOURCES - 1, 2); in build_madt()
588 build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); in build_madt()
591 /* Global System Interrupt Vector Base */ in build_madt()
602 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
603 * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
612 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); in build_srat()
613 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, in build_srat()
614 .oem_table_id = vms->oem_table_id }; in build_srat()
620 for (i = 0; i < cpu_list->len; ++i) { in build_srat()
621 uint32_t nodeid = cpu_list->cpus[i].props.node_id; in build_srat()
630 /* Flags, Table 5-70 */ in build_srat()
635 mem_base = vms->memmap[VIRT_DRAM].base; in build_srat()
636 for (i = 0; i < ms->numa_state->num_nodes; ++i) { in build_srat()
637 if (ms->numa_state->nodes[i].node_mem > 0) { in build_srat()
639 ms->numa_state->nodes[i].node_mem, i, in build_srat()
641 mem_base += ms->numa_state->nodes[i].node_mem; in build_srat()
652 GArray *tables_blob = tables->table_data; in virt_acpi_build()
658 bios_linker_loader_alloc(tables->linker, in virt_acpi_build()
663 dsdt = tables_blob->len; in virt_acpi_build()
664 build_dsdt(tables_blob, tables->linker, s); in virt_acpi_build()
668 build_fadt_rev6(tables_blob, tables->linker, s, dsdt); in virt_acpi_build()
671 build_madt(tables_blob, tables->linker, s); in virt_acpi_build()
674 build_rhct(tables_blob, tables->linker, s); in virt_acpi_build()
677 spcr_setup(tables_blob, tables->linker, s); in virt_acpi_build()
682 .base = s->memmap[VIRT_PCIE_ECAM].base, in virt_acpi_build()
683 .size = s->memmap[VIRT_PCIE_ECAM].size, in virt_acpi_build()
685 build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, in virt_acpi_build()
686 s->oem_table_id); in virt_acpi_build()
689 if (ms->numa_state->num_nodes > 0) { in virt_acpi_build()
691 build_srat(tables_blob, tables->linker, s); in virt_acpi_build()
692 if (ms->numa_state->have_numa_distance) { in virt_acpi_build()
694 build_slit(tables_blob, tables->linker, ms, s->oem_id, in virt_acpi_build()
695 s->oem_table_id); in virt_acpi_build()
700 xsdt = tables_blob->len; in virt_acpi_build()
701 build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, in virt_acpi_build()
702 s->oem_table_id); in virt_acpi_build()
708 .oem_id = s->oem_id, in virt_acpi_build()
712 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); in virt_acpi_build()
719 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { in virt_acpi_build()
722 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); in virt_acpi_build()
737 * Make sure RAM size is correct - in case it got changed in acpi_ram_update()
742 memcpy(memory_region_get_ram_ptr(mr), data->data, size); in acpi_ram_update()
752 if (!build_state || build_state->patched) { in virt_acpi_build_update()
756 build_state->patched = true; in virt_acpi_build_update()
762 acpi_ram_update(build_state->table_mr, tables.table_data); in virt_acpi_build_update()
763 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); in virt_acpi_build_update()
764 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); in virt_acpi_build_update()
772 build_state->patched = false; in virt_acpi_build_reset()
796 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, in virt_acpi_setup()
799 assert(build_state->table_mr != NULL); in virt_acpi_setup()
801 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, in virt_acpi_setup()
803 tables.linker->cmd_blob, in virt_acpi_setup()
806 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, in virt_acpi_setup()