Lines Matching +full:0 +full:x10060000
10 * 0) UART
69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
78 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
79 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
80 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
81 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
82 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
93 #define GEM_REVISION 0x10070109
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
127 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); in create_fdt()
129 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); in create_fdt()
130 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); in create_fdt()
140 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
151 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
166 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
167 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
169 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { in create_fdt()
174 /* cpu 0 is the management hart that does not have mmu */ in create_fdt()
175 if (cpu != 0) { in create_fdt()
183 riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); in create_fdt()
192 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); in create_fdt()
199 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt()
203 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); in create_fdt()
215 0x0, memmap[SIFIVE_U_DEV_CLINT].base, in create_fdt()
216 0x0, memmap[SIFIVE_U_DEV_CLINT].size); in create_fdt()
227 0x0, memmap[SIFIVE_U_DEV_OTP].base, in create_fdt()
228 0x0, memmap[SIFIVE_U_DEV_OTP].size); in create_fdt()
238 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); in create_fdt()
242 0x0, memmap[SIFIVE_U_DEV_PRCI].base, in create_fdt()
243 0x0, memmap[SIFIVE_U_DEV_PRCI].size); in create_fdt()
250 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt()
254 /* cpu 0 is the management hart that does not have S-mode */ in create_fdt()
255 if (cpu == 0) { in create_fdt()
256 cells[0] = cpu_to_be32(intc_phandle); in create_fdt()
261 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); in create_fdt()
272 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); in create_fdt()
276 0x0, memmap[SIFIVE_U_DEV_PLIC].base, in create_fdt()
277 0x0, memmap[SIFIVE_U_DEV_PLIC].size); in create_fdt()
293 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); in create_fdt()
295 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); in create_fdt()
297 0x0, memmap[SIFIVE_U_DEV_GPIO].base, in create_fdt()
298 0x0, memmap[SIFIVE_U_DEV_GPIO].size); in create_fdt()
325 0x0, memmap[SIFIVE_U_DEV_PDMA].base, in create_fdt()
326 0x0, memmap[SIFIVE_U_DEV_PDMA].size); in create_fdt()
335 0x0, memmap[SIFIVE_U_DEV_L2CC].base, in create_fdt()
336 0x0, memmap[SIFIVE_U_DEV_L2CC].size); in create_fdt()
340 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); in create_fdt()
352 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
359 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, in create_fdt()
360 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); in create_fdt()
364 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", in create_fdt()
367 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); in create_fdt()
370 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); in create_fdt()
377 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
384 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, in create_fdt()
385 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); in create_fdt()
389 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", in create_fdt()
394 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); in create_fdt()
396 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); in create_fdt()
407 0x0, memmap[SIFIVE_U_DEV_GEM].base, in create_fdt()
408 0x0, memmap[SIFIVE_U_DEV_GEM].size, in create_fdt()
409 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, in create_fdt()
410 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); in create_fdt()
423 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
430 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", in create_fdt()
434 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); in create_fdt()
442 0x0, memmap[SIFIVE_U_DEV_PWM0].base, in create_fdt()
443 0x0, memmap[SIFIVE_U_DEV_PWM0].size); in create_fdt()
450 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
458 0x0, memmap[SIFIVE_U_DEV_PWM1].base, in create_fdt()
459 0x0, memmap[SIFIVE_U_DEV_PWM1].size); in create_fdt()
466 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
474 0x0, memmap[SIFIVE_U_DEV_UART1].base, in create_fdt()
475 0x0, memmap[SIFIVE_U_DEV_UART1].size); in create_fdt()
489 0x0, memmap[SIFIVE_U_DEV_UART0].base, in create_fdt()
490 0x0, memmap[SIFIVE_U_DEV_UART0].size); in create_fdt()
520 uint32_t start_addr_hi32 = 0x00000000; in sifive_u_machine_init()
549 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); in sifive_u_machine_init()
604 kernel_entry = 0; in sifive_u_machine_init()
619 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ in sifive_u_machine_init()
620 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ in sifive_u_machine_init()
621 0xf1402573, /* csrr a0, mhartid */ in sifive_u_machine_init()
622 0, in sifive_u_machine_init()
623 0, in sifive_u_machine_init()
624 0x00028067, /* jr t0 */ in sifive_u_machine_init()
628 0x00000000, in sifive_u_machine_init()
629 0x00000000, in sifive_u_machine_init()
633 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ in sifive_u_machine_init()
634 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ in sifive_u_machine_init()
636 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ in sifive_u_machine_init()
637 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ in sifive_u_machine_init()
642 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { in sifive_u_machine_init()
655 dinfo = drive_get(IF_MTD, 0, 0); in sifive_u_machine_init()
663 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); in sifive_u_machine_init()
669 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); in sifive_u_machine_init()
672 dinfo = drive_get(IF_SD, 0, 0); in sifive_u_machine_init()
700 s->msel = 0; in sifive_u_machine_instance_init()
704 "Mode Select (MSEL[3:0]) pin state"); in sifive_u_machine_instance_init()
753 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); in type_init()
758 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); in type_init()
760 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); in type_init()
775 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); in type_init()
793 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); in sifive_u_soc_realize()
831 plic_hart_config, ms->smp.cpus, 0, in sifive_u_soc_realize()
843 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); in sifive_u_soc_realize()
846 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, in sifive_u_soc_realize()
850 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in sifive_u_soc_realize()
857 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); in sifive_u_soc_realize()
863 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); in sifive_u_soc_realize()
869 for (i = 0; i < 16; i++) { in sifive_u_soc_realize()
877 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); in sifive_u_soc_realize()
880 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { in sifive_u_soc_realize()
890 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); in sifive_u_soc_realize()
898 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); in sifive_u_soc_realize()
899 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, in sifive_u_soc_realize()
903 for (i = 0; i < 2; i++) { in sifive_u_soc_realize()
907 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, in sifive_u_soc_realize()
908 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); in sifive_u_soc_realize()
911 for (j = 0; j < SIFIVE_PWM_IRQS; j++) { in sifive_u_soc_realize()
928 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, in sifive_u_soc_realize()
930 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, in sifive_u_soc_realize()
933 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, in sifive_u_soc_realize()
935 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, in sifive_u_soc_realize()