hw/riscv/sifive_u.c

100     void *fdt;
114     fdt = ms->fdt = create_device_tree(&s->fdt_size);
115     if (!fdt) {
120     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
121     qemu_fdt_setprop_string(fdt, "/", "compatible",
123     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
124     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
126     qemu_fdt_add_subnode(fdt, "/soc");
127     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
128     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
129     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
130     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
134     qemu_fdt_add_subnode(fdt, nodename);
135     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
136     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
137     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
139     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
140     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
145     qemu_fdt_add_subnode(fdt, nodename);
146     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
147     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
148     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
150     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
151     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
156     qemu_fdt_add_subnode(fdt, nodename);
157     qemu_fdt_setprop_cells(fdt, nodename, "reg",
160     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
163     qemu_fdt_add_subnode(fdt, "/cpus");
164     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
166     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
167     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
173         qemu_fdt_add_subnode(fdt, nodename);
177                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
179                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv39");
181             riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename);
183             riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename);
185         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
186         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
187         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
188         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
189         qemu_fdt_add_subnode(fdt, intc);
190         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
191         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
192         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
193         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
202         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
211     qemu_fdt_add_subnode(fdt, nodename);
212     qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
214     qemu_fdt_setprop_cells(fdt, nodename, "reg",
217     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
224     qemu_fdt_add_subnode(fdt, nodename);
225     qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
226     qemu_fdt_setprop_cells(fdt, nodename, "reg",
229     qemu_fdt_setprop_string(fdt, nodename, "compatible",
236     qemu_fdt_add_subnode(fdt, nodename);
237     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
238     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
239     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
241     qemu_fdt_setprop_cells(fdt, nodename, "reg",
244     qemu_fdt_setprop_string(fdt, nodename, "compatible",
253         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
268     qemu_fdt_add_subnode(fdt, nodename);
269     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
270     qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
272     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
273     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
275     qemu_fdt_setprop_cells(fdt, nodename, "reg",
278     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
280     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
281     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
288     qemu_fdt_add_subnode(fdt, nodename);
289     qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
290     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
292     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
293     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
294     qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
295     qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
296     qemu_fdt_setprop_cells(fdt, nodename, "reg",
299     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
305     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
306     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
310     qemu_fdt_add_subnode(fdt, nodename);
311     qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
312     qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
317     qemu_fdt_add_subnode(fdt, nodename);
318     qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
319     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
323     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
324     qemu_fdt_setprop_cells(fdt, nodename, "reg",
327     qemu_fdt_setprop_string(fdt, nodename, "compatible",
333     qemu_fdt_add_subnode(fdt, nodename);
334     qemu_fdt_setprop_cells(fdt, nodename, "reg",
337     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
339     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
340     qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
341     qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
342     qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
343     qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
344     qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
345     qemu_fdt_setprop_string(fdt, nodename, "compatible",
351     qemu_fdt_add_subnode(fdt, nodename);
352     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
353     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
354     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
356     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
357     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
358     qemu_fdt_setprop_cells(fdt, nodename, "reg",
361     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
366     qemu_fdt_add_subnode(fdt, nodename);
367     qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
368     qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
369     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
370     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
371     qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
376     qemu_fdt_add_subnode(fdt, nodename);
377     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
378     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
379     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
381     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
382     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
383     qemu_fdt_setprop_cells(fdt, nodename, "reg",
386     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
391     qemu_fdt_add_subnode(fdt, nodename);
392     qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
393     qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
394     qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
395     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
396     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
397     qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
403     qemu_fdt_add_subnode(fdt, nodename);
404     qemu_fdt_setprop_string(fdt, nodename, "compatible",
406     qemu_fdt_setprop_cells(fdt, nodename, "reg",
411     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
412     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
413     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
414     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
415     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
416     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
418     qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
420     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
422     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
423     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
425     qemu_fdt_add_subnode(fdt, "/aliases");
426     qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
432     qemu_fdt_add_subnode(fdt, nodename);
433     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
434     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
439     qemu_fdt_add_subnode(fdt, nodename);
440     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
441     qemu_fdt_setprop_cells(fdt, nodename, "reg",
444     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
445     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
448     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
450     qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
455     qemu_fdt_add_subnode(fdt, nodename);
456     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
457     qemu_fdt_setprop_cells(fdt, nodename, "reg",
460     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
461     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
464     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
466     qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
471     qemu_fdt_add_subnode(fdt, nodename);
472     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
473     qemu_fdt_setprop_cells(fdt, nodename, "reg",
476     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
478     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
479     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
481     qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
486     qemu_fdt_add_subnode(fdt, nodename);
487     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
488     qemu_fdt_setprop_cells(fdt, nodename, "reg",
491     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
493     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
494     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
496     qemu_fdt_add_subnode(fdt, "/chosen");
497     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
498     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
555         machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
556         if (!machine->fdt) {
613     riscv_load_fdt(fdt_load_addr, machine->fdt);