hw/riscv/riscv-iommu.h

2  * QEMU emulation of an RISC-V IOMMU
4  * Copyright (C) 2022-2023 Rivos Inc.
23 #include "hw/qdev-properties.h"
24 #include "system/dma.h"
26 #include "hw/riscv/riscv-iommu-bits.h"
37     uint32_t bus;         /* PCI bus mapping for non-root endpoints */
43     bool enable_off;      /* Enable out-of-reset OFF mode (DMA disabled) */
46     bool enable_s_stage;  /* Enable S/VS-Stage translation */
47     bool enable_g_stage;  /* Enable G-Stage translation */
79     uint8_t *regs_wc;  /* write-1-to-clear mask */
80     uint8_t *regs_ro;  /* read-only mask */
107     uint64_t tc;                /* Translation Control */
109     uint64_t satp;              /* S-Stage address translation and protection */
110     uint64_t gatp;              /* G-Stage address translation and protection */
111     uint64_t msi_addr_mask;     /* MSI filtering - address mask */
112     uint64_t msi_addr_pattern;  /* MSI filtering - address pattern */
122     uint32_t val = ldl_le_p(s->regs_rw + idx);  in riscv_iommu_reg_mod32()
123     stl_le_p(s->regs_rw + idx, (val & ~clr) | set);  in riscv_iommu_reg_mod32()
130     stl_le_p(s->regs_rw + idx, set);  in riscv_iommu_reg_set32()
135     return ldl_le_p(s->regs_rw + idx);  in riscv_iommu_reg_get32()
141     uint64_t val = ldq_le_p(s->regs_rw + idx);  in riscv_iommu_reg_mod64()
142     stq_le_p(s->regs_rw + idx, (val & ~clr) | set);  in riscv_iommu_reg_mod64()
149     stq_le_p(s->regs_rw + idx, set);  in riscv_iommu_reg_set64()
155     return ldq_le_p(s->regs_rw + idx);  in riscv_iommu_reg_get64()