Lines Matching refs:pass
272 } pass; in riscv_iommu_spa_fetch() local
310 for (pass = 0; pass < 2; pass++) { in riscv_iommu_spa_fetch()
313 sc[pass].step = 0; in riscv_iommu_spa_fetch()
314 if (pass ? (s->fctl & RISCV_IOMMU_FCTL_GXL) : in riscv_iommu_spa_fetch()
317 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
319 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
320 sc[pass].ptidxbits = 0; in riscv_iommu_spa_fetch()
321 sc[pass].ptesize = 0; in riscv_iommu_spa_fetch()
324 sv_mode = pass ? RISCV_IOMMU_CAP_SV32X4 : RISCV_IOMMU_CAP_SV32; in riscv_iommu_spa_fetch()
328 sc[pass].levels = 2; in riscv_iommu_spa_fetch()
329 sc[pass].ptidxbits = 10; in riscv_iommu_spa_fetch()
330 sc[pass].ptesize = 4; in riscv_iommu_spa_fetch()
337 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
339 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
340 sc[pass].ptidxbits = 0; in riscv_iommu_spa_fetch()
341 sc[pass].ptesize = 0; in riscv_iommu_spa_fetch()
344 sv_mode = pass ? RISCV_IOMMU_CAP_SV39X4 : RISCV_IOMMU_CAP_SV39; in riscv_iommu_spa_fetch()
348 sc[pass].levels = 3; in riscv_iommu_spa_fetch()
349 sc[pass].ptidxbits = 9; in riscv_iommu_spa_fetch()
350 sc[pass].ptesize = 8; in riscv_iommu_spa_fetch()
353 sv_mode = pass ? RISCV_IOMMU_CAP_SV48X4 : RISCV_IOMMU_CAP_SV48; in riscv_iommu_spa_fetch()
357 sc[pass].levels = 4; in riscv_iommu_spa_fetch()
358 sc[pass].ptidxbits = 9; in riscv_iommu_spa_fetch()
359 sc[pass].ptesize = 8; in riscv_iommu_spa_fetch()
362 sv_mode = pass ? RISCV_IOMMU_CAP_SV57X4 : RISCV_IOMMU_CAP_SV57; in riscv_iommu_spa_fetch()
366 sc[pass].levels = 5; in riscv_iommu_spa_fetch()
367 sc[pass].ptidxbits = 9; in riscv_iommu_spa_fetch()
368 sc[pass].ptesize = 8; in riscv_iommu_spa_fetch()
381 pass = en_g ? G_STAGE : S_STAGE; in riscv_iommu_spa_fetch()
384 const unsigned widened = (pass && !sc[pass].step) ? 2 : 0; in riscv_iommu_spa_fetch()
385 const unsigned va_bits = widened + sc[pass].ptidxbits; in riscv_iommu_spa_fetch()
386 const unsigned va_skip = TARGET_PAGE_BITS + sc[pass].ptidxbits * in riscv_iommu_spa_fetch()
387 (sc[pass].levels - 1 - sc[pass].step); in riscv_iommu_spa_fetch()
389 const dma_addr_t pte_addr = base + idx * sc[pass].ptesize; in riscv_iommu_spa_fetch()
391 ctx->tc & (pass ? RISCV_IOMMU_DC_TC_GADE : RISCV_IOMMU_DC_TC_SADE); in riscv_iommu_spa_fetch()
394 if (!sc[pass].step) { in riscv_iommu_spa_fetch()
402 if (sc[pass].ptesize == 4) { in riscv_iommu_spa_fetch()
416 sc[pass].step++; in riscv_iommu_spa_fetch()
439 sc[pass].step = sc[pass].levels; in riscv_iommu_spa_fetch()
444 if (pass && sc[0].step != sc[0].levels) { in riscv_iommu_spa_fetch()
445 pass = S_STAGE; in riscv_iommu_spa_fetch()
455 if (pass == S_STAGE && (iotlb->perm & IOMMU_WO) && in riscv_iommu_spa_fetch()
464 if (!pass && en_g) { in riscv_iommu_spa_fetch()
465 pass = G_STAGE; in riscv_iommu_spa_fetch()
468 sc[pass].step = 0; in riscv_iommu_spa_fetch()
475 if (sc[pass].step == sc[pass].levels) { in riscv_iommu_spa_fetch()
480 if (!pass && en_g) { in riscv_iommu_spa_fetch()
481 pass = G_STAGE; in riscv_iommu_spa_fetch()
484 sc[pass].step = 0; in riscv_iommu_spa_fetch()
489 (pass ? RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS : in riscv_iommu_spa_fetch()
491 (pass ? RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS : in riscv_iommu_spa_fetch()