Lines Matching +full:0 +full:x40460000
41 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
42 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
43 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
44 [IBEX_DEV_UART] = { 0x40000000, 0x40 },
45 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
46 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
47 [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
48 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
49 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
50 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
51 [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
52 [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
53 [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
54 [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
55 [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
56 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
57 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
58 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
59 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
60 [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
61 [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
62 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
63 [IBEX_DEV_AES] = { 0x41100000, 0x100 },
64 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
65 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
66 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
67 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
68 [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
69 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
70 [IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
71 [IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
72 [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
73 [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
74 [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
75 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
136 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { in lowrisc_ibex_soc_init()
170 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, in lowrisc_ibex_soc_realize()
181 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); in lowrisc_ibex_soc_realize()
182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); in lowrisc_ibex_soc_realize()
191 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); in lowrisc_ibex_soc_realize()
193 for (i = 0; i < ms->smp.cpus; i++) { in lowrisc_ibex_soc_realize()
201 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); in lowrisc_ibex_soc_realize()
205 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); in lowrisc_ibex_soc_realize()
207 0, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
222 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); in lowrisc_ibex_soc_realize()
224 0, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
226 qdev_connect_gpio_out(DEVICE(&s->timer), 0, in lowrisc_ibex_soc_realize()
227 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), in lowrisc_ibex_soc_realize()
231 for (i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { in lowrisc_ibex_soc_realize()
237 sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); in lowrisc_ibex_soc_realize()
241 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
247 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
310 DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),