Lines Matching +full:load +full:- +full:reduced
2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
60 * See https://github.com/polarfire-soc/hart-software-services
74 * https://www.microsemi.com/document-portal/doc_download/
75 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
79 * https://www.microsemi.com/document-portal/doc_download/
80 * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
81 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
83 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
149 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); in microchip_pfsoc_soc_instance_init()
150 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); in microchip_pfsoc_soc_instance_init()
152 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, in microchip_pfsoc_soc_instance_init()
154 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); in microchip_pfsoc_soc_instance_init()
155 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); in microchip_pfsoc_soc_instance_init()
156 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", in microchip_pfsoc_soc_instance_init()
158 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); in microchip_pfsoc_soc_instance_init()
160 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); in microchip_pfsoc_soc_instance_init()
161 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); in microchip_pfsoc_soc_instance_init()
163 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, in microchip_pfsoc_soc_instance_init()
165 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); in microchip_pfsoc_soc_instance_init()
166 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); in microchip_pfsoc_soc_instance_init()
167 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", in microchip_pfsoc_soc_instance_init()
169 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); in microchip_pfsoc_soc_instance_init()
171 object_initialize_child(obj, "dma-controller", &s->dma, in microchip_pfsoc_soc_instance_init()
174 object_initialize_child(obj, "sysreg", &s->sysreg, in microchip_pfsoc_soc_instance_init()
177 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, in microchip_pfsoc_soc_instance_init()
179 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, in microchip_pfsoc_soc_instance_init()
182 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); in microchip_pfsoc_soc_instance_init()
183 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); in microchip_pfsoc_soc_instance_init()
185 object_initialize_child(obj, "sd-controller", &s->sdhci, in microchip_pfsoc_soc_instance_init()
188 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); in microchip_pfsoc_soc_instance_init()
206 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); in microchip_pfsoc_soc_realize()
207 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); in microchip_pfsoc_soc_realize()
209 * The cluster must be realized after the RISC-V hart array container, in microchip_pfsoc_soc_realize()
214 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); in microchip_pfsoc_soc_realize()
215 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); in microchip_pfsoc_soc_realize()
250 0, ms->smp.cpus, false); in microchip_pfsoc_soc_realize()
253 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in microchip_pfsoc_soc_realize()
255 iks->clint_timebase_freq, false); in microchip_pfsoc_soc_realize()
262 * Add L2-LIM at reset size. in microchip_pfsoc_soc_realize()
263 * This should be reduced in size as the L2 Cache Controller WayEnable in microchip_pfsoc_soc_realize()
277 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); in microchip_pfsoc_soc_realize()
280 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, in microchip_pfsoc_soc_realize()
281 plic_hart_config, ms->smp.cpus, 0, in microchip_pfsoc_soc_realize()
294 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); in microchip_pfsoc_soc_realize()
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, in microchip_pfsoc_soc_realize()
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, in microchip_pfsoc_soc_realize()
299 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
304 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); in microchip_pfsoc_soc_realize()
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
308 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
327 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); in microchip_pfsoc_soc_realize()
328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, in microchip_pfsoc_soc_realize()
332 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); in microchip_pfsoc_soc_realize()
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, in microchip_pfsoc_soc_realize()
337 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); in microchip_pfsoc_soc_realize()
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
341 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); in microchip_pfsoc_soc_realize()
344 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
346 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), in microchip_pfsoc_soc_realize()
348 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
350 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), in microchip_pfsoc_soc_realize()
352 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
354 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), in microchip_pfsoc_soc_realize()
356 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
358 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), in microchip_pfsoc_soc_realize()
360 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
362 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), in microchip_pfsoc_soc_realize()
412 qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL); in microchip_pfsoc_soc_realize()
413 qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL); in microchip_pfsoc_soc_realize()
415 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); in microchip_pfsoc_soc_realize()
416 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); in microchip_pfsoc_soc_realize()
417 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); in microchip_pfsoc_soc_realize()
418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
421 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); in microchip_pfsoc_soc_realize()
423 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); in microchip_pfsoc_soc_realize()
424 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); in microchip_pfsoc_soc_realize()
425 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); in microchip_pfsoc_soc_realize()
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
429 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); in microchip_pfsoc_soc_realize()
451 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); in microchip_pfsoc_soc_realize()
452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
455 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
485 dc->realize = microchip_pfsoc_soc_realize; in microchip_pfsoc_soc_class_init()
487 dc->user_creatable = false; in microchip_pfsoc_soc_class_init()
525 if (machine->ram_size < mc->default_ram_size) { in type_init()
526 char *sz = size_to_str(mc->default_ram_size); in type_init()
533 object_initialize_child(OBJECT(machine), "soc", &s->soc, in type_init()
535 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in type_init()
537 /* Split RAM into low and high regions using aliases to machine->ram */ in type_init()
539 mem_high_size = machine->ram_size - mem_low_size; in type_init()
541 "microchip.icicle.kit.ram_low", machine->ram, in type_init()
544 "microchip.icicle.kit.ram_high", machine->ram, in type_init()
571 CadenceSDHCIState *sdhci = &(s->soc.sdhci); in type_init()
576 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); in type_init()
582 * -bios | -kernel | firmware in type_init()
583 * --------------+------------+-------- in type_init()
590 if (machine->firmware && !strcmp(machine->firmware, "none")) { in type_init()
591 if (!machine->kernel_filename) { in type_init()
592 error_report("for -bios none, a kernel is required"); in type_init()
598 } else if (!machine->firmware || !strcmp(machine->firmware, "default")) { in type_init()
599 if (machine->kernel_filename) { in type_init()
607 firmware_name = machine->firmware; in type_init()
611 /* Load the firmware if necessary */ in type_init()
622 riscv_boot_info_init(&boot_info, &s->soc.u_cpus); in type_init()
623 if (machine->kernel_filename) { in type_init()
631 if (machine->dtb) { in type_init()
633 machine->fdt = load_device_tree(machine->dtb, &fdt_size); in type_init()
634 if (!machine->fdt) { in type_init()
639 /* Compute the FDT load address in DRAM */ in type_init()
643 if (kernel_entry - kernel_ram_base >= kernel_ram_size) { in type_init()
650 riscv_load_fdt(fdt_load_addr, machine->fdt); in type_init()
652 warn_report_once("The QEMU microchip-icicle-kit machine does not " in type_init()
665 /* Load the reset vector */ in type_init()
666 riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, start_addr, in type_init()
686 s->clint_timebase_freq = value; in microchip_icicle_kit_set_clint_timebase_freq()
696 uint32_t value = s->clint_timebase_freq; in microchip_icicle_kit_get_clint_timebase_freq()
704 m->clint_timebase_freq = 1000000; in microchip_icicle_kit_machine_instance_init()
712 mc->desc = "Microchip PolarFire SoC Icicle Kit"; in microchip_icicle_kit_machine_class_init()
713 mc->init = microchip_icicle_kit_machine_init; in microchip_icicle_kit_machine_class_init()
714 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + in microchip_icicle_kit_machine_class_init()
716 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; in microchip_icicle_kit_machine_class_init()
717 mc->default_cpus = mc->min_cpus; in microchip_icicle_kit_machine_class_init()
718 mc->default_ram_id = "microchip.icicle.kit.ram"; in microchip_icicle_kit_machine_class_init()
719 mc->auto_create_sdcard = true; in microchip_icicle_kit_machine_class_init()
728 mc->default_ram_size = 1537 * MiB; in microchip_icicle_kit_machine_class_init()
730 object_class_property_add(oc, "clint-timebase-frequency", "uint32_t", in microchip_icicle_kit_machine_class_init()
734 object_class_property_set_description(oc, "clint-timebase-frequency", in microchip_icicle_kit_machine_class_init()
739 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),