35     MAL0_CFG      = 0x180,
36     MAL0_ESR      = 0x181,
37     MAL0_IER      = 0x182,
38     MAL0_TXCASR   = 0x184,
39     MAL0_TXCARR   = 0x185,
40     MAL0_TXEOBISR = 0x186,
41     MAL0_TXDEIR   = 0x187,
42     MAL0_RXCASR   = 0x190,
43     MAL0_RXCARR   = 0x191,
44     MAL0_RXEOBISR = 0x192,
45     MAL0_RXDEIR   = 0x193,
46     MAL0_TXCTP0R  = 0x1A0,
47     MAL0_RXCTP0R  = 0x1C0,
48     MAL0_RCBS0    = 0x1E0,
49     MAL0_RCBS1    = 0x1E1,
56     mal->cfg = 0x0007C000;  in ppc4xx_mal_reset()
57     mal->esr = 0x00000000;  in ppc4xx_mal_reset()
58     mal->ier = 0x00000000;  in ppc4xx_mal_reset()
59     mal->rxcasr = 0x00000000;  in ppc4xx_mal_reset()
60     mal->rxdeir = 0x00000000;  in ppc4xx_mal_reset()
61     mal->rxeobisr = 0x00000000;  in ppc4xx_mal_reset()
62     mal->txcasr = 0x00000000;  in ppc4xx_mal_reset()
63     mal->txdeir = 0x00000000;  in ppc4xx_mal_reset()
64     mal->txeobisr = 0x00000000;  in ppc4xx_mal_reset()
107         ret = 0;  in dcr_read_mal()
129         if (val & 0x80000000) {  in dcr_write_mal()
132         mal->cfg = val & 0x00FFC087;  in dcr_write_mal()
139         mal->ier = val & 0x0000001F;  in dcr_write_mal()
142         mal->txcasr = val & 0xF0000000;  in dcr_write_mal()
145         mal->txcarr = val & 0xF0000000;  in dcr_write_mal()
156         mal->rxcasr = val & 0xC0000000;  in dcr_write_mal()
159         mal->rxcarr = val & 0xC0000000;  in dcr_write_mal()
177         mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;  in dcr_write_mal()
196     for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {  in ppc4xx_mal_realize()
211     for (i = 0; i < mal->txcnum; i++) {  in ppc4xx_mal_realize()
215     for (i = 0; i < mal->rxcnum; i++) {  in ppc4xx_mal_realize()
219     for (i = 0; i < mal->rxcnum; i++) {  in ppc4xx_mal_realize()
235     DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
236     DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
254     PLB3A0_ACR = 0x077,
255     PLB4A0_ACR = 0x081,
256     PLB0_BESR  = 0x084,
257     PLB0_BEAR  = 0x086,
258     PLB0_ACR   = 0x087,
259     PLB4A1_ACR = 0x089,
279         ret = 0;  in dcr_read_plb()
296         plb->acr = val & 0xF8000000;  in dcr_write_plb()
312     plb->acr = 0x00000000;  in ppc405_plb_reset()
313     plb->bear = 0x00000000;  in ppc405_plb_reset()
314     plb->besr = 0x00000000;  in ppc405_plb_reset()
343     EBC0_CFGADDR = 0x012,
344     EBC0_CFGDATA = 0x013,
358         case 0x00: /* B0CR */  in dcr_read_ebc()
359             ret = ebc->bcr[0];  in dcr_read_ebc()
361         case 0x01: /* B1CR */  in dcr_read_ebc()
364         case 0x02: /* B2CR */  in dcr_read_ebc()
367         case 0x03: /* B3CR */  in dcr_read_ebc()
370         case 0x04: /* B4CR */  in dcr_read_ebc()
373         case 0x05: /* B5CR */  in dcr_read_ebc()
376         case 0x06: /* B6CR */  in dcr_read_ebc()
379         case 0x07: /* B7CR */  in dcr_read_ebc()
382         case 0x10: /* B0AP */  in dcr_read_ebc()
383             ret = ebc->bap[0];  in dcr_read_ebc()
385         case 0x11: /* B1AP */  in dcr_read_ebc()
388         case 0x12: /* B2AP */  in dcr_read_ebc()
391         case 0x13: /* B3AP */  in dcr_read_ebc()
394         case 0x14: /* B4AP */  in dcr_read_ebc()
397         case 0x15: /* B5AP */  in dcr_read_ebc()
400         case 0x16: /* B6AP */  in dcr_read_ebc()
403         case 0x17: /* B7AP */  in dcr_read_ebc()
406         case 0x20: /* BEAR */  in dcr_read_ebc()
409         case 0x21: /* BESR0 */  in dcr_read_ebc()
412         case 0x22: /* BESR1 */  in dcr_read_ebc()
415         case 0x23: /* CFG */  in dcr_read_ebc()
419             ret = 0x00000000;  in dcr_read_ebc()
424         ret = 0x00000000;  in dcr_read_ebc()
441         case 0x00: /* B0CR */  in dcr_write_ebc()
443         case 0x01: /* B1CR */  in dcr_write_ebc()
445         case 0x02: /* B2CR */  in dcr_write_ebc()
447         case 0x03: /* B3CR */  in dcr_write_ebc()
449         case 0x04: /* B4CR */  in dcr_write_ebc()
451         case 0x05: /* B5CR */  in dcr_write_ebc()
453         case 0x06: /* B6CR */  in dcr_write_ebc()
455         case 0x07: /* B7CR */  in dcr_write_ebc()
457         case 0x10: /* B0AP */  in dcr_write_ebc()
459         case 0x11: /* B1AP */  in dcr_write_ebc()
461         case 0x12: /* B2AP */  in dcr_write_ebc()
463         case 0x13: /* B3AP */  in dcr_write_ebc()
465         case 0x14: /* B4AP */  in dcr_write_ebc()
467         case 0x15: /* B5AP */  in dcr_write_ebc()
469         case 0x16: /* B6AP */  in dcr_write_ebc()
471         case 0x17: /* B7AP */  in dcr_write_ebc()
473         case 0x20: /* BEAR */  in dcr_write_ebc()
475         case 0x21: /* BESR0 */  in dcr_write_ebc()
477         case 0x22: /* BESR1 */  in dcr_write_ebc()
479         case 0x23: /* CFG */  in dcr_write_ebc()
495     ebc->addr = 0x00000000;  in ppc405_ebc_reset()
496     ebc->bap[0] = 0x7F8FFE80;  in ppc405_ebc_reset()
497     ebc->bcr[0] = 0xFFE28000;  in ppc405_ebc_reset()
498     for (i = 0; i < 8; i++) {  in ppc405_ebc_reset()
499         ebc->bap[i] = 0x00000000;  in ppc405_ebc_reset()
500         ebc->bcr[i] = 0x00000000;  in ppc405_ebc_reset()
502     ebc->besr0 = 0x00000000;  in ppc405_ebc_reset()
503     ebc->besr1 = 0x00000000;  in ppc405_ebc_reset()
504     ebc->cfg = 0x80400000;  in ppc405_ebc_reset()