240     ppc4xx_cpr_t *cpr = opaque;  in dcr_read_cpr()  local
245         ret = cpr->addr;  in dcr_read_cpr()
248         switch (cpr->addr) {  in dcr_read_cpr()
275     ppc4xx_cpr_t *cpr = opaque;  in dcr_write_cpr()  local
279         cpr->addr = val;  in dcr_write_cpr()
290     ppc4xx_cpr_t *cpr = opaque;  in ppc4xx_cpr_reset()  local
292     cpr->addr = 0;  in ppc4xx_cpr_reset()
297     ppc4xx_cpr_t *cpr;  in ppc4xx_cpr_init()  local
299     cpr = g_malloc0(sizeof(*cpr));  in ppc4xx_cpr_init()
300     ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);  in ppc4xx_cpr_init()
301     ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);  in ppc4xx_cpr_init()
302     qemu_register_reset(ppc4xx_cpr_reset, cpr);  in ppc4xx_cpr_init()