Lines Matching full:cpc

753 static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)  in ppc405ep_compute_clocks()  argument
761 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { in ppc405ep_compute_clocks()
762 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ in ppc405ep_compute_clocks()
763 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); in ppc405ep_compute_clocks()
764 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ in ppc405ep_compute_clocks()
765 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); in ppc405ep_compute_clocks()
766 VCO_out = (uint64_t)cpc->sysclk * M * D; in ppc405ep_compute_clocks()
772 cpc->pllmr[1] &= ~0x80000000; in ppc405ep_compute_clocks()
778 cpc->boot |= 0x00000001; in ppc405ep_compute_clocks()
783 PLL_out = cpc->sysclk; in ppc405ep_compute_clocks()
784 if (cpc->pllmr[1] & 0x40000000) { in ppc405ep_compute_clocks()
786 cpc->boot &= ~0x00000001; in ppc405ep_compute_clocks()
790 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ in ppc405ep_compute_clocks()
791 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); in ppc405ep_compute_clocks()
793 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ in ppc405ep_compute_clocks()
794 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); in ppc405ep_compute_clocks()
796 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ in ppc405ep_compute_clocks()
797 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); in ppc405ep_compute_clocks()
799 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ in ppc405ep_compute_clocks()
800 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); in ppc405ep_compute_clocks()
802 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ in ppc405ep_compute_clocks()
803 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); in ppc405ep_compute_clocks()
805 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ in ppc405ep_compute_clocks()
806 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); in ppc405ep_compute_clocks()
808 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ in ppc405ep_compute_clocks()
809 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); in ppc405ep_compute_clocks()
811 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ in ppc405ep_compute_clocks()
812 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); in ppc405ep_compute_clocks()
822 cpc->sysclk, VCO_out, PLL_out, in ppc405ep_compute_clocks()
829 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); in ppc405ep_compute_clocks()
831 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); in ppc405ep_compute_clocks()
833 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); in ppc405ep_compute_clocks()
835 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); in ppc405ep_compute_clocks()
837 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); in ppc405ep_compute_clocks()
839 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); in ppc405ep_compute_clocks()
841 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); in ppc405ep_compute_clocks()
843 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); in ppc405ep_compute_clocks()
848 Ppc405CpcState *cpc = opaque; in dcr_read_epcpc() local
853 ret = cpc->boot; in dcr_read_epcpc()
856 ret = cpc->epctl; in dcr_read_epcpc()
859 ret = cpc->pllmr[0]; in dcr_read_epcpc()
862 ret = cpc->pllmr[1]; in dcr_read_epcpc()
865 ret = cpc->ucr; in dcr_read_epcpc()
868 ret = cpc->srr; in dcr_read_epcpc()
871 ret = cpc->jtagid; in dcr_read_epcpc()
874 ret = cpc->pci; in dcr_read_epcpc()
887 Ppc405CpcState *cpc = opaque; in dcr_write_epcpc() local
895 cpc->epctl = val & 0xC00000F3; in dcr_write_epcpc()
898 cpc->pllmr[0] = val & 0x00633333; in dcr_write_epcpc()
899 ppc405ep_compute_clocks(cpc); in dcr_write_epcpc()
902 cpc->pllmr[1] = val & 0xC0F73FFF; in dcr_write_epcpc()
903 ppc405ep_compute_clocks(cpc); in dcr_write_epcpc()
907 cpc->ucr = val & 0x003F7F7F; in dcr_write_epcpc()
910 cpc->srr = val; in dcr_write_epcpc()
916 cpc->pci = val; in dcr_write_epcpc()
923 Ppc405CpcState *cpc = PPC405_CPC(dev); in ppc405_cpc_reset() local
925 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ in ppc405_cpc_reset()
926 cpc->epctl = 0x00000000; in ppc405_cpc_reset()
927 cpc->pllmr[0] = 0x00021002; in ppc405_cpc_reset()
928 cpc->pllmr[1] = 0x80a552be; in ppc405_cpc_reset()
929 cpc->ucr = 0x00004646; in ppc405_cpc_reset()
930 cpc->srr = 0x00040000; in ppc405_cpc_reset()
931 cpc->pci = 0x00000000; in ppc405_cpc_reset()
932 cpc->er = 0x00000000; in ppc405_cpc_reset()
933 cpc->fr = 0x00000000; in ppc405_cpc_reset()
934 cpc->sr = 0x00000000; in ppc405_cpc_reset()
935 cpc->jtagid = 0x20267049; in ppc405_cpc_reset()
936 ppc405ep_compute_clocks(cpc); in ppc405_cpc_reset()
942 Ppc405CpcState *cpc = PPC405_CPC(dev); in ppc405_cpc_realize() local
946 cpc->clk_setup[PPC405EP_CPU_CLK].cb = in ppc405_cpc_realize()
947 ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT); in ppc405_cpc_realize()
948 cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env; in ppc405_cpc_realize()
950 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc, in ppc405_cpc_realize()
952 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc, in ppc405_cpc_realize()
954 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc, in ppc405_cpc_realize()
956 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc, in ppc405_cpc_realize()
958 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc, in ppc405_cpc_realize()
960 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc, in ppc405_cpc_realize()
962 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc, in ppc405_cpc_realize()
964 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc, in ppc405_cpc_realize()
995 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); in ppc405_soc_instance_init()
996 object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); in ppc405_soc_instance_init()
1045 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) { in ppc405_soc_realize()