Lines Matching refs:bd
126 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, in ppc405_set_default_bootinfo() argument
129 memset(bd, 0, sizeof(*bd)); in ppc405_set_default_bootinfo()
131 bd->bi_memstart = PPC405EP_SDRAM_BASE; in ppc405_set_default_bootinfo()
132 bd->bi_memsize = ram_size; in ppc405_set_default_bootinfo()
133 bd->bi_sramstart = PPC405EP_SRAM_BASE; in ppc405_set_default_bootinfo()
134 bd->bi_sramsize = PPC405EP_SRAM_SIZE; in ppc405_set_default_bootinfo()
135 bd->bi_bootflags = 0; in ppc405_set_default_bootinfo()
136 bd->bi_intfreq = 133333333; in ppc405_set_default_bootinfo()
137 bd->bi_busfreq = 33333333; in ppc405_set_default_bootinfo()
138 bd->bi_baudrate = 115200; in ppc405_set_default_bootinfo()
139 bd->bi_s_version[0] = 'Q'; in ppc405_set_default_bootinfo()
140 bd->bi_s_version[1] = 'M'; in ppc405_set_default_bootinfo()
141 bd->bi_s_version[2] = 'U'; in ppc405_set_default_bootinfo()
142 bd->bi_s_version[3] = '\0'; in ppc405_set_default_bootinfo()
143 bd->bi_r_version[0] = 'Q'; in ppc405_set_default_bootinfo()
144 bd->bi_r_version[1] = 'E'; in ppc405_set_default_bootinfo()
145 bd->bi_r_version[2] = 'M'; in ppc405_set_default_bootinfo()
146 bd->bi_r_version[3] = 'U'; in ppc405_set_default_bootinfo()
147 bd->bi_r_version[4] = '\0'; in ppc405_set_default_bootinfo()
148 bd->bi_procfreq = 133333333; in ppc405_set_default_bootinfo()
149 bd->bi_plb_busfreq = 33333333; in ppc405_set_default_bootinfo()
150 bd->bi_pci_busfreq = 33333333; in ppc405_set_default_bootinfo()
151 bd->bi_opbfreq = 33333333; in ppc405_set_default_bootinfo()
154 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) in __ppc405_set_bootinfo() argument
161 if (bd->bi_memsize >= 0x01000000UL) { in __ppc405_set_bootinfo()
164 bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t); in __ppc405_set_bootinfo()
166 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); in __ppc405_set_bootinfo()
167 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); in __ppc405_set_bootinfo()
168 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); in __ppc405_set_bootinfo()
169 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); in __ppc405_set_bootinfo()
170 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); in __ppc405_set_bootinfo()
171 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); in __ppc405_set_bootinfo()
172 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); in __ppc405_set_bootinfo()
173 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); in __ppc405_set_bootinfo()
174 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); in __ppc405_set_bootinfo()
176 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); in __ppc405_set_bootinfo()
178 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); in __ppc405_set_bootinfo()
179 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); in __ppc405_set_bootinfo()
180 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); in __ppc405_set_bootinfo()
181 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); in __ppc405_set_bootinfo()
183 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); in __ppc405_set_bootinfo()
186 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); in __ppc405_set_bootinfo()
188 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); in __ppc405_set_bootinfo()
189 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); in __ppc405_set_bootinfo()
190 stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); in __ppc405_set_bootinfo()
192 stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); in __ppc405_set_bootinfo()
196 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); in __ppc405_set_bootinfo()
198 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); in __ppc405_set_bootinfo()
201 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); in __ppc405_set_bootinfo()
210 ppc4xx_bd_info_t bd; in ppc405_set_bootinfo() local
212 memset(&bd, 0, sizeof(bd)); in ppc405_set_bootinfo()
214 ppc405_set_default_bootinfo(&bd, ram_size); in ppc405_set_bootinfo()
216 return __ppc405_set_bootinfo(env, &bd); in ppc405_set_bootinfo()