Lines Matching +full:edge +full:- +full:sensitive
4 * Copyright (c) 2003-2007 Jocelyn Mayer
32 #include "qemu/main-loop.h"
33 #include "qemu/error-report.h"
46 CPUPPCState *env = &cpu->env; in ppc_set_irq()
52 old_pending = env->pending_interrupts; in ppc_set_irq()
55 env->pending_interrupts |= irq; in ppc_set_irq()
57 env->pending_interrupts &= ~irq; in ppc_set_irq()
60 if (old_pending != env->pending_interrupts) { in ppc_set_irq()
67 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, in ppc_set_irq()
68 CPU(cpu)->interrupt_request); in ppc_set_irq()
75 CPUPPCState *env = &cpu->env; in ppc6xx_set_irq()
80 cur_level = (env->irq_input_state >> pin) & 1; in ppc6xx_set_irq()
87 /* Level sensitive - active high */ in ppc6xx_set_irq()
96 /* Level sensitive - active high */ in ppc6xx_set_irq()
101 /* Level sensitive - active high */ in ppc6xx_set_irq()
106 /* Negative edge sensitive */ in ppc6xx_set_irq()
116 /* Level sensitive - active low */ in ppc6xx_set_irq()
121 cs->halted = 1; in ppc6xx_set_irq()
125 /* Level sensitive - active low */ in ppc6xx_set_irq()
139 env->irq_input_state |= 1 << pin; in ppc6xx_set_irq()
141 env->irq_input_state &= ~(1 << pin); in ppc6xx_set_irq()
155 CPUPPCState *env = &cpu->env; in ppc970_set_irq()
160 cur_level = (env->irq_input_state >> pin) & 1; in ppc970_set_irq()
167 /* Level sensitive - active high */ in ppc970_set_irq()
172 /* Level sensitive - active high */ in ppc970_set_irq()
177 /* Negative edge sensitive */ in ppc970_set_irq()
187 /* Level sensitive - active low */ in ppc970_set_irq()
191 cs->halted = 1; in ppc970_set_irq()
194 cs->halted = 0; in ppc970_set_irq()
199 /* Level sensitive - active low */ in ppc970_set_irq()
216 env->irq_input_state |= 1 << pin; in ppc970_set_irq()
218 env->irq_input_state &= ~(1 << pin); in ppc970_set_irq()
232 trace_ppc_irq_set(&cpu->env, pin, level); in power7_set_irq()
236 /* Level sensitive - active high */ in power7_set_irq()
255 trace_ppc_irq_set(&cpu->env, pin, level); in power9_set_irq()
259 /* Level sensitive - active high */ in power9_set_irq()
264 /* Level sensitive - active high */ in power9_set_irq()
281 CPUPPCState *env = &cpu->env; in ppc40x_core_reset()
286 dbsr = env->spr[SPR_40x_DBSR]; in ppc40x_core_reset()
289 env->spr[SPR_40x_DBSR] = dbsr; in ppc40x_core_reset()
294 CPUPPCState *env = &cpu->env; in ppc40x_chip_reset()
300 dbsr = env->spr[SPR_40x_DBSR]; in ppc40x_chip_reset()
303 env->spr[SPR_40x_DBSR] = dbsr; in ppc40x_chip_reset()
343 CPUPPCState *env = &cpu->env; in ppc40x_set_irq()
348 cur_level = (env->irq_input_state >> pin) & 1; in ppc40x_set_irq()
374 /* Level sensitive - active high */ in ppc40x_set_irq()
379 /* Level sensitive - active high */ in ppc40x_set_irq()
384 /* Level sensitive - active low */ in ppc40x_set_irq()
387 cs->halted = 1; in ppc40x_set_irq()
390 cs->halted = 0; in ppc40x_set_irq()
395 /* Level sensitive - active high */ in ppc40x_set_irq()
403 env->irq_input_state |= 1 << pin; in ppc40x_set_irq()
405 env->irq_input_state &= ~(1 << pin); in ppc40x_set_irq()
418 CPUPPCState *env = &cpu->env; in ppce500_set_irq()
423 cur_level = (env->irq_input_state >> pin) & 1; in ppce500_set_irq()
440 /* Level sensitive - active high */ in ppce500_set_irq()
445 /* Level sensitive - active high */ in ppce500_set_irq()
450 /* Level sensitive - active high */ in ppce500_set_irq()
458 env->irq_input_state |= 1 << pin; in ppce500_set_irq()
460 env->irq_input_state &= ~(1 << pin); in ppce500_set_irq()
477 cpu->env.mpic_proxy = enabled; in ppce500_set_mpic_proxy()
512 return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset; in cpu_ppc_get_tb()
517 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_load_tbl()
521 return env->spr[SPR_TBL]; in cpu_ppc_load_tbl()
525 tb_env->tb_offset); in cpu_ppc_load_tbl()
533 ppc_tb_t *tb_env = env->tb_env; in _cpu_ppc_load_tbu()
537 tb_env->tb_offset); in _cpu_ppc_load_tbu()
546 return env->spr[SPR_TBU]; in cpu_ppc_load_tbu()
555 *tb_offsetp = value - ns_to_tb(tb_env->tb_freq, vmclk); in cpu_ppc_store_tb()
562 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_store_tbl()
566 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); in cpu_ppc_store_tbl()
568 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb | (uint64_t)value); in cpu_ppc_store_tbl()
573 ppc_tb_t *tb_env = env->tb_env; in _cpu_ppc_store_tbu()
577 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); in _cpu_ppc_store_tbu()
579 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, in _cpu_ppc_store_tbu()
590 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_load_atbl()
594 tb_env->atb_offset); in cpu_ppc_load_atbl()
602 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_load_atbu()
606 tb_env->atb_offset); in cpu_ppc_load_atbu()
614 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_store_atbl()
618 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset); in cpu_ppc_store_atbl()
620 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, tb | (uint64_t)value); in cpu_ppc_store_atbl()
625 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_store_atbu()
629 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset); in cpu_ppc_store_atbu()
631 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, in cpu_ppc_store_atbu()
637 env->tb_env->tb_offset += offset; in cpu_ppc_increase_tb_by_offset()
642 env->tb_env->tb_offset -= offset; in cpu_ppc_decrease_tb_by_offset()
647 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_load_vtb()
650 tb_env->vtb_offset); in cpu_ppc_load_vtb()
655 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_store_vtb()
658 &tb_env->vtb_offset, value); in cpu_ppc_store_vtb()
663 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_store_tbu40()
667 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); in cpu_ppc_store_tbu40()
670 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb); in cpu_ppc_store_tbu40()
675 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_tb_stop()
679 if (tb_env->tb_freq != 0) { in cpu_ppc_tb_stop()
682 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); in cpu_ppc_tb_stop()
684 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); in cpu_ppc_tb_stop()
686 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); in cpu_ppc_tb_stop()
688 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); in cpu_ppc_tb_stop()
690 tb_env->tb_freq = 0; in cpu_ppc_tb_stop()
697 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_tb_start()
701 if (tb_env->tb_freq == 0) { in cpu_ppc_tb_start()
704 tb = tb_env->tb_offset; in cpu_ppc_tb_start()
706 atb = tb_env->atb_offset; in cpu_ppc_tb_start()
708 tb_env->tb_freq = tb_env->decr_freq; in cpu_ppc_tb_start()
710 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); in cpu_ppc_tb_start()
712 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); in cpu_ppc_tb_start()
718 ppc_tb_t *tb_env = env->tb_env; in ppc_decr_clear_on_delivery()
720 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); in ppc_decr_clear_on_delivery()
726 ppc_tb_t *tb_env = env->tb_env; in __cpu_ppc_load_decr()
730 n = ns_to_tb(tb_env->decr_freq, now); in __cpu_ppc_load_decr()
733 if (next < n && tb_env->flags & PPC_TIMER_BOOKE) { in __cpu_ppc_load_decr()
736 decr = next - n; in __cpu_ppc_load_decr()
746 ppc_tb_t *tb_env = env->tb_env; in _cpu_ppc_load_decr()
749 decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next); in _cpu_ppc_load_decr()
755 if (env->spr[SPR_LPCR] & LPCR_LD) { in _cpu_ppc_load_decr()
758 return sextract64(decr, 0, pcc->lrg_decr_bits); in _cpu_ppc_load_decr()
766 return env->spr[SPR_DECR]; in cpu_ppc_load_decr()
776 ppc_tb_t *tb_env = env->tb_env; in _cpu_ppc_load_hdecr()
779 hdecr = __cpu_ppc_load_decr(env, now, tb_env->hdecr_next); in _cpu_ppc_load_hdecr()
785 if (pcc->lrg_decr_bits > 32) { in _cpu_ppc_load_hdecr()
786 return sextract64(hdecr, 0, pcc->lrg_decr_bits); in _cpu_ppc_load_hdecr()
798 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_load_purr()
801 tb_env->purr_offset); in cpu_ppc_load_purr()
821 CPUPPCState *env = &cpu->env; in cpu_ppc_hdecr_excp()
830 if (!env->resume_as_sreset) { in cpu_ppc_hdecr_excp()
847 CPUPPCState *env = &cpu->env; in __cpu_ppc_store_decr()
848 ppc_tb_t *tb_env = env->tb_env; in __cpu_ppc_store_decr()
867 next = ns_to_tb(tb_env->decr_freq, now) + value; in __cpu_ppc_store_decr()
871 * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt. in __cpu_ppc_store_decr()
876 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers in __cpu_ppc_store_decr()
877 * an edge interrupt, so raise it here too. in __cpu_ppc_store_decr()
892 timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next)); in __cpu_ppc_store_decr()
899 ppc_tb_t *tb_env = cpu->env.tb_env; in _cpu_ppc_store_decr()
901 __cpu_ppc_store_decr(cpu, now, &tb_env->decr_next, tb_env->decr_timer, in _cpu_ppc_store_decr()
902 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, in _cpu_ppc_store_decr()
903 tb_env->flags, decr, value, nr_bits); in _cpu_ppc_store_decr()
919 if (env->spr[SPR_LPCR] & LPCR_LD) { in cpu_ppc_store_decr()
920 nr_bits = pcc->lrg_decr_bits; in cpu_ppc_store_decr()
939 ppc_tb_t *tb_env = cpu->env.tb_env; in _cpu_ppc_store_hdecr()
941 if (tb_env->hdecr_timer != NULL) { in _cpu_ppc_store_hdecr()
942 /* HDECR (Book3S 64bit) is edge-based, not level like DECR */ in _cpu_ppc_store_hdecr()
943 __cpu_ppc_store_decr(cpu, now, &tb_env->hdecr_next, tb_env->hdecr_timer, in _cpu_ppc_store_hdecr()
944 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, in _cpu_ppc_store_hdecr()
959 _cpu_ppc_store_hdecr(cpu, now, hdecr, value, pcc->lrg_decr_bits); in cpu_ppc_store_hdecr()
971 ppc_tb_t *tb_env = env->tb_env; in _cpu_ppc_store_purr()
973 cpu_ppc_store_tb(tb_env, now, &tb_env->purr_offset, value); in _cpu_ppc_store_purr()
986 if (!first_ppc_cpu->env.tb_env) { in timebase_save()
993 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); in timebase_save()
995 /* simpler for record-replay to avoid this event, compat not needed */ in timebase_save()
996 tb->time_of_the_day_ns = 0; in timebase_save()
1003 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; in timebase_save()
1005 tb->runstate_paused = in timebase_save()
1016 if (!first_ppc_cpu->env.tb_env) { in timebase_load()
1021 freq = first_ppc_cpu->env.tb_env->tb_freq; in timebase_load()
1023 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); in timebase_load()
1025 tb_off = first_ppc_cpu->env.tb_env->tb_offset; in timebase_load()
1026 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, in timebase_load()
1027 (tb_off_adj - tb_off) / freq); in timebase_load()
1032 pcpu->env.tb_env->tb_offset = tb_off_adj; in timebase_load()
1033 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); in timebase_load()
1068 if (!tb->runstate_paused) { in timebase_pre_save()
1094 env->tb_env = tb_env; in cpu_ppc_tb_init()
1095 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; in cpu_ppc_tb_init()
1098 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; in cpu_ppc_tb_init()
1101 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in cpu_ppc_tb_init()
1103 if (env->has_hv_mode && !cpu->vhyp) { in cpu_ppc_tb_init()
1104 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in cpu_ppc_tb_init()
1107 tb_env->hdecr_timer = NULL; in cpu_ppc_tb_init()
1110 tb_env->tb_freq = freq; in cpu_ppc_tb_init()
1111 tb_env->decr_freq = freq; in cpu_ppc_tb_init()
1117 ppc_tb_t *tb_env = env->tb_env; in cpu_ppc_tb_reset()
1119 timer_del(tb_env->decr_timer); in cpu_ppc_tb_reset()
1121 tb_env->decr_next = 0; in cpu_ppc_tb_reset()
1122 if (tb_env->hdecr_timer != NULL) { in cpu_ppc_tb_reset()
1123 timer_del(tb_env->hdecr_timer); in cpu_ppc_tb_reset()
1125 tb_env->hdecr_next = 0; in cpu_ppc_tb_reset()
1133 cpu_ppc_store_decr(env, -1); in cpu_ppc_tb_reset()
1134 cpu_ppc_store_hdecr(env, -1); in cpu_ppc_tb_reset()
1140 timer_free(env->tb_env->decr_timer); in cpu_ppc_tb_free()
1141 timer_free(env->tb_env->hdecr_timer); in cpu_ppc_tb_free()
1142 g_free(env->tb_env); in cpu_ppc_tb_free()
1150 assert(env->tb_env->hdecr_timer == NULL); in cpu_ppc_hdecr_init()
1152 env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in cpu_ppc_hdecr_init()
1160 timer_free(env->tb_env->hdecr_timer); in cpu_ppc_hdecr_exit()
1161 env->tb_env->hdecr_timer = NULL; in cpu_ppc_hdecr_exit()
1172 uint64_t pit_reload; /* PIT auto-reload value */
1186 CPUPPCState *env = &cpu->env; in cpu_4xx_fit_cb()
1191 tb_env = env->tb_env; in cpu_4xx_fit_cb()
1192 ppc40x_timer = tb_env->opaque; in cpu_4xx_fit_cb()
1194 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { in cpu_4xx_fit_cb()
1211 next = now + tb_to_ns_round_up(tb_env->tb_freq, next); in cpu_4xx_fit_cb()
1212 timer_mod(ppc40x_timer->fit_timer, next); in cpu_4xx_fit_cb()
1213 env->spr[SPR_40x_TSR] |= 1 << 26; in cpu_4xx_fit_cb()
1214 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { in cpu_4xx_fit_cb()
1217 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), in cpu_4xx_fit_cb()
1218 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); in cpu_4xx_fit_cb()
1227 ppc40x_timer = tb_env->opaque; in start_stop_pit()
1228 if (ppc40x_timer->pit_reload <= 1 || in start_stop_pit()
1229 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || in start_stop_pit()
1230 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { in start_stop_pit()
1233 timer_del(tb_env->decr_timer); in start_stop_pit()
1235 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload); in start_stop_pit()
1239 tb_env->decr_next += ppc40x_timer->pit_reload; in start_stop_pit()
1241 tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now) in start_stop_pit()
1242 + ppc40x_timer->pit_reload; in start_stop_pit()
1244 next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next); in start_stop_pit()
1245 timer_mod(tb_env->decr_timer, next); in start_stop_pit()
1252 CPUPPCState *env = &cpu->env; in cpu_4xx_pit_cb()
1256 tb_env = env->tb_env; in cpu_4xx_pit_cb()
1257 ppc40x_timer = tb_env->opaque; in cpu_4xx_pit_cb()
1258 env->spr[SPR_40x_TSR] |= 1 << 27; in cpu_4xx_pit_cb()
1259 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { in cpu_4xx_pit_cb()
1260 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); in cpu_4xx_pit_cb()
1263 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), in cpu_4xx_pit_cb()
1264 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), in cpu_4xx_pit_cb()
1265 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], in cpu_4xx_pit_cb()
1266 ppc40x_timer->pit_reload); in cpu_4xx_pit_cb()
1273 CPUPPCState *env = &cpu->env; in cpu_4xx_wdt_cb()
1278 tb_env = env->tb_env; in cpu_4xx_wdt_cb()
1279 ppc40x_timer = tb_env->opaque; in cpu_4xx_wdt_cb()
1281 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { in cpu_4xx_wdt_cb()
1298 next = now + tb_to_ns_round_up(tb_env->decr_freq, next); in cpu_4xx_wdt_cb()
1299 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); in cpu_4xx_wdt_cb()
1300 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { in cpu_4xx_wdt_cb()
1303 timer_mod(ppc40x_timer->wdt_timer, next); in cpu_4xx_wdt_cb()
1304 ppc40x_timer->wdt_next = next; in cpu_4xx_wdt_cb()
1305 env->spr[SPR_40x_TSR] |= 1U << 31; in cpu_4xx_wdt_cb()
1308 timer_mod(ppc40x_timer->wdt_timer, next); in cpu_4xx_wdt_cb()
1309 ppc40x_timer->wdt_next = next; in cpu_4xx_wdt_cb()
1310 env->spr[SPR_40x_TSR] |= 1 << 30; in cpu_4xx_wdt_cb()
1311 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { in cpu_4xx_wdt_cb()
1316 env->spr[SPR_40x_TSR] &= ~0x30000000; in cpu_4xx_wdt_cb()
1317 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; in cpu_4xx_wdt_cb()
1318 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { in cpu_4xx_wdt_cb()
1340 tb_env = env->tb_env; in store_40x_pit()
1341 ppc40x_timer = tb_env->opaque; in store_40x_pit()
1343 ppc40x_timer->pit_reload = val; in store_40x_pit()
1358 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); in store_40x_tsr()
1371 tb_env = env->tb_env; in store_40x_tcr()
1372 env->spr[SPR_40x_TCR] = val & 0xFFC00000; in store_40x_tcr()
1380 ppc_tb_t *tb_env = env->tb_env; in ppc_40x_set_tb_clk()
1383 tb_env->tb_freq = freq; in ppc_40x_set_tb_clk()
1384 tb_env->decr_freq = freq; in ppc_40x_set_tb_clk()
1400 env->tb_env = tb_env; in ppc_40x_timers_init()
1401 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; in ppc_40x_timers_init()
1402 tb_env->tb_freq = freq; in ppc_40x_timers_init()
1403 tb_env->decr_freq = freq; in ppc_40x_timers_init()
1404 tb_env->opaque = ppc40x_timer; in ppc_40x_timers_init()
1407 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu); in ppc_40x_timers_init()
1408 ppc40x_timer->fit_timer = in ppc_40x_timers_init()
1410 ppc40x_timer->wdt_timer = in ppc_40x_timers_init()
1412 ppc40x_timer->decr_excp = decr_excp; in ppc_40x_timers_init()
1442 dcr = &dcr_env->dcrn[dcrn]; in ppc_dcr_read()
1443 if (dcr->dcr_read == NULL) in ppc_dcr_read()
1445 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); in ppc_dcr_read()
1451 if (dcr_env->read_error != NULL) in ppc_dcr_read()
1452 return (*dcr_env->read_error)(dcrn); in ppc_dcr_read()
1454 return -1; in ppc_dcr_read()
1463 dcr = &dcr_env->dcrn[dcrn]; in ppc_dcr_write()
1464 if (dcr->dcr_write == NULL) in ppc_dcr_write()
1467 (*dcr->dcr_write)(dcr->opaque, dcrn, val); in ppc_dcr_write()
1472 if (dcr_env->write_error != NULL) in ppc_dcr_write()
1473 return (*dcr_env->write_error)(dcrn); in ppc_dcr_write()
1475 return -1; in ppc_dcr_write()
1484 dcr_env = env->dcr_env; in ppc_dcr_register()
1486 return -1; in ppc_dcr_register()
1488 return -1; in ppc_dcr_register()
1489 dcr = &dcr_env->dcrn[dcrn]; in ppc_dcr_register()
1490 if (dcr->opaque != NULL || in ppc_dcr_register()
1491 dcr->dcr_read != NULL || in ppc_dcr_register()
1492 dcr->dcr_write != NULL) in ppc_dcr_register()
1493 return -1; in ppc_dcr_register()
1494 dcr->opaque = opaque; in ppc_dcr_register()
1495 dcr->dcr_read = dcr_read; in ppc_dcr_register()
1496 dcr->dcr_write = dcr_write; in ppc_dcr_register()
1507 dcr_env->read_error = read_error; in ppc_dcr_init()
1508 dcr_env->write_error = write_error; in ppc_dcr_init()
1509 env->dcr_env = dcr_env; in ppc_dcr_init()
1518 CPUPPCState *env = &cpu->env; in ppc_cpu_pir()
1519 return env->spr_cb[SPR_PIR].default_value; in ppc_cpu_pir()
1524 CPUPPCState *env = &cpu->env; in ppc_cpu_tir()
1525 return env->spr_cb[SPR_TIR].default_value; in ppc_cpu_tir()
1545 CPUPPCState *env = &cpu->env; in ppc_irq_reset()
1547 env->irq_input_state = 0; in ppc_irq_reset()