Lines Matching +full:ls +full:- +full:bits
27 #include "hw/qdev-properties.h"
43 /* OPB Master LS registers */
70 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
105 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; in pnv_lpc_dt_xscom()
120 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_lpc_dt_xscom()
121 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_lpc_dt_xscom()
130 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; in pnv_dt_lpc()
131 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; in pnv_dt_lpc()
163 name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); in pnv_dt_lpc()
169 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); in pnv_dt_lpc()
170 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1))); in pnv_dt_lpc()
172 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id))); in pnv_dt_lpc()
179 name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR); in pnv_dt_lpc()
188 "ibm,power9-lpcm-opb-master"))); in pnv_dt_lpc()
193 name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR); in pnv_dt_lpc()
202 "ibm,power9-lpcm-opb-arbiter"))); in pnv_dt_lpc()
207 name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR); in pnv_dt_lpc()
216 "ibm,power9-lpc-controller"))); in pnv_dt_lpc()
222 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_dt_lpc()
223 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_dt_lpc()
243 return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_opb_read()
251 return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_opb_write()
256 #define ECCB_CTL_SZ_LSH (63 - 7)
262 #define ECCB_STAT_RD_DATA_LSH (63 - 37)
267 /* XXX Check for magic bits at the top, addr size etc... */ in pnv_lpc_do_eccb()
282 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | in pnv_lpc_do_eccb()
288 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | in pnv_lpc_do_eccb()
292 data[0] = lpc->eccb_data_reg >> 24; in pnv_lpc_do_eccb()
293 data[1] = lpc->eccb_data_reg >> 16; in pnv_lpc_do_eccb()
294 data[2] = lpc->eccb_data_reg >> 8; in pnv_lpc_do_eccb()
295 data[3] = lpc->eccb_data_reg; in pnv_lpc_do_eccb()
298 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; in pnv_lpc_do_eccb()
315 val = lpc->eccb_stat_reg; in pnv_lpc_xscom_read()
316 lpc->eccb_stat_reg = 0; in pnv_lpc_xscom_read()
319 val = ((uint64_t)lpc->eccb_data_reg) << 32; in pnv_lpc_xscom_read()
341 lpc->eccb_data_reg = val >> 32; in pnv_lpc_xscom_write()
367 val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_mmio_read()
371 val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_mmio_read()
398 address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_mmio_write()
402 address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, in pnv_lpc_mmio_write()
433 if (!lpc->psi_has_serirq) { in pnv_lpc_eval_serirq_routes()
434 if ((lpc->opb_irq_route0 & PPC_BITMASK32(8, 13)) || in pnv_lpc_eval_serirq_routes()
435 (lpc->opb_irq_route1 & PPC_BITMASK32(4, 31))) { in pnv_lpc_eval_serirq_routes()
444 * bits, split across 2 OPB registers. in pnv_lpc_eval_serirq_routes()
447 int serirq = extract32(lpc->opb_irq_route1, in pnv_lpc_eval_serirq_routes()
449 lpc->irq_to_serirq_route[irq] = serirq; in pnv_lpc_eval_serirq_routes()
453 int serirq = extract32(lpc->opb_irq_route0, in pnv_lpc_eval_serirq_routes()
454 PPC_BIT32_NR(9 + (irq - 14) * 2), 2); in pnv_lpc_eval_serirq_routes()
455 lpc->irq_to_serirq_route[irq] = serirq; in pnv_lpc_eval_serirq_routes()
463 active_irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; in pnv_lpc_eval_irqs()
464 if (!(lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN)) { in pnv_lpc_eval_irqs()
469 if (lpc->psi_has_serirq) { in pnv_lpc_eval_irqs()
481 serirq_out[lpc->irq_to_serirq_route[irq]] = true; in pnv_lpc_eval_irqs()
485 qemu_set_irq(lpc->psi_irq_serirq[0], serirq_out[0]); in pnv_lpc_eval_irqs()
486 qemu_set_irq(lpc->psi_irq_serirq[1], serirq_out[1]); in pnv_lpc_eval_irqs()
487 qemu_set_irq(lpc->psi_irq_serirq[2], serirq_out[2]); in pnv_lpc_eval_irqs()
488 qemu_set_irq(lpc->psi_irq_serirq[3], serirq_out[3]); in pnv_lpc_eval_irqs()
507 lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; in pnv_lpc_eval_irqs()
509 lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; in pnv_lpc_eval_irqs()
513 lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; in pnv_lpc_eval_irqs()
515 qemu_set_irq(lpc->psi_irq_lpchc, lpc->opb_irq_stat != 0); in pnv_lpc_eval_irqs()
520 lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SYNC_NORESP_ERR; in pnv_lpc_opb_noresponse()
531 val = lpc->lpc_hc_fw_seg_idsel; in lpc_hc_read()
534 val = lpc->lpc_hc_fw_rd_acc_size; in lpc_hc_read()
537 val = lpc->lpc_hc_irqser_ctrl; in lpc_hc_read()
540 val = lpc->lpc_hc_irqmask; in lpc_hc_read()
543 val = lpc->lpc_hc_irqstat; in lpc_hc_read()
546 val = lpc->lpc_hc_error_addr; in lpc_hc_read()
560 /* XXX Filter out reserved bits */ in lpc_hc_write()
568 val &= 0xf; /* Selects device 0-15 */ in lpc_hc_write()
569 lpc->lpc_hc_fw_seg_idsel = val; in lpc_hc_write()
570 memory_region_set_alias_offset(&lpc->opb_isa_fw, val * LPC_FW_OPB_SIZE); in lpc_hc_write()
573 lpc->lpc_hc_fw_rd_acc_size = val; in lpc_hc_write()
576 lpc->lpc_hc_irqser_ctrl = val; in lpc_hc_write()
580 lpc->lpc_hc_irqmask = val; in lpc_hc_write()
585 * This register is write-to-clear for the IRQSER (LPC device IRQ) in lpc_hc_write()
586 * status. However if the device has not de-asserted its interrupt in lpc_hc_write()
591 lpc->lpc_hc_irqstat &= ~(val & ~lpc->lpc_hc_irq_inputs); in lpc_hc_write()
623 val = lpc->opb_irq_route0; in opb_master_read()
626 val = lpc->opb_irq_route1; in opb_master_read()
629 val = lpc->opb_irq_stat; in opb_master_read()
632 val = lpc->opb_irq_mask; in opb_master_read()
635 val = lpc->opb_irq_pol; in opb_master_read()
638 val = lpc->opb_irq_input; in opb_master_read()
655 lpc->opb_irq_route0 = val; in opb_master_write()
660 lpc->opb_irq_route1 = val; in opb_master_write()
665 lpc->opb_irq_stat &= ~val; in opb_master_write()
669 lpc->opb_irq_mask = val; in opb_master_write()
673 lpc->opb_irq_pol = val; in opb_master_write()
705 plc->parent_realize(dev, &local_err); in pnv_lpc_power8_realize()
712 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc), in pnv_lpc_power8_realize()
713 &pnv_lpc_xscom_ops, lpc, "xscom-lpc", in pnv_lpc_power8_realize()
723 dc->desc = "PowerNV LPC Controller POWER8"; in pnv_lpc_power8_class_init()
725 xdc->dt_xscom = pnv_lpc_dt_xscom; in pnv_lpc_power8_class_init()
728 &plc->parent_realize); in pnv_lpc_power8_class_init()
747 object_property_set_bool(OBJECT(lpc), "psi-serirq", true, &error_abort); in pnv_lpc_power9_realize()
749 plc->parent_realize(dev, &local_err); in pnv_lpc_power9_realize()
756 memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, in pnv_lpc_power9_realize()
760 qdev_init_gpio_out_named(dev, lpc->psi_irq_serirq, "SERIRQ", 4); in pnv_lpc_power9_realize()
768 dc->desc = "PowerNV LPC Controller POWER9"; in pnv_lpc_power9_class_init()
771 &plc->parent_realize); in pnv_lpc_power9_class_init()
784 dc->desc = "PowerNV LPC Controller POWER10"; in pnv_lpc_power10_class_init()
798 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; in pnv_lpc_realize()
801 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); in pnv_lpc_realize()
802 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); in pnv_lpc_realize()
808 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); in pnv_lpc_realize()
809 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); in pnv_lpc_realize()
810 memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE); in pnv_lpc_realize()
813 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", in pnv_lpc_realize()
814 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); in pnv_lpc_realize()
815 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, in pnv_lpc_realize()
816 &lpc->opb_isa_io); in pnv_lpc_realize()
817 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", in pnv_lpc_realize()
818 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); in pnv_lpc_realize()
819 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, in pnv_lpc_realize()
820 &lpc->opb_isa_mem); in pnv_lpc_realize()
821 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", in pnv_lpc_realize()
822 &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); in pnv_lpc_realize()
823 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, in pnv_lpc_realize()
824 &lpc->opb_isa_fw); in pnv_lpc_realize()
827 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, in pnv_lpc_realize()
828 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); in pnv_lpc_realize()
829 lpc->opb_master_regs.disable_reentrancy_guard = true; in pnv_lpc_realize()
830 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, in pnv_lpc_realize()
831 &lpc->opb_master_regs); in pnv_lpc_realize()
832 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, in pnv_lpc_realize()
833 "lpc-hc", LPC_HC_REGS_OPB_SIZE); in pnv_lpc_realize()
834 /* xscom writes to lpc-hc. As such mark lpc-hc re-entrancy safe */ in pnv_lpc_realize()
835 lpc->lpc_hc_regs.disable_reentrancy_guard = true; in pnv_lpc_realize()
836 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, in pnv_lpc_realize()
837 &lpc->lpc_hc_regs); in pnv_lpc_realize()
839 qdev_init_gpio_out_named(dev, &lpc->psi_irq_lpchc, "LPCHC", 1); in pnv_lpc_realize()
843 DEFINE_PROP_BOOL("psi-serirq", PnvLpcController, psi_has_serirq, false),
851 dc->realize = pnv_lpc_realize; in pnv_lpc_class_init()
852 dc->desc = "PowerNV LPC Controller"; in pnv_lpc_class_init()
853 dc->user_creatable = false; in pnv_lpc_class_init()
875 /* If we don't use the built-in LPC interrupt deserializer, we need in type_init()
878 * Most machines using pre-Naples chips (without said deserializer) in type_init()
886 uint32_t old_state = pnv->cpld_irqstate; in type_init()
890 pnv->cpld_irqstate |= 1u << n; in type_init()
892 pnv->cpld_irqstate &= ~(1u << n); in type_init()
895 if (pnv->cpld_irqstate != old_state) { in type_init()
896 qemu_set_irq(lpc->psi_irq_lpchc, pnv->cpld_irqstate != 0); in type_init()
906 lpc->lpc_hc_irq_inputs |= irq_bit; in pnv_lpc_isa_irq_handler()
913 lpc->lpc_hc_irqstat |= irq_bit; in pnv_lpc_isa_irq_handler()
916 lpc->lpc_hc_irq_inputs &= ~irq_bit; in pnv_lpc_isa_irq_handler()
918 /* POWER9 adds an auto-clear mode that clears IRQSTAT bits on EOI */ in pnv_lpc_isa_irq_handler()
919 if (lpc->psi_has_serirq && in pnv_lpc_isa_irq_handler()
920 (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_AUTO_CLEAR)) { in pnv_lpc_isa_irq_handler()
921 lpc->lpc_hc_irqstat &= ~irq_bit; in pnv_lpc_isa_irq_handler()
938 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err); in pnv_lpc_isa_create()