Lines Matching +full:hb +full:- +full:ahci
43 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci-host/pnv_phb.h"
46 #include "hw/pci-host/pnv_phb3.h"
47 #include "hw/pci-host/pnv_phb4.h"
50 #include "hw/qdev-properties.h"
56 #include "hw/char/serial-isa.h"
75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); in pnv_chip_core_typename()
110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); in pnv_dt_memory()
120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); in get_cpus_node()
121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); in get_cpus_node()
137 PowerPCCPU *cpu = pc->threads[0]; in pnv_dt_core()
140 int smt_threads = CPU_CORE(pc)->nr_threads; in pnv_dt_core()
141 CPUPPCState *env = &cpu->env; in pnv_dt_core()
157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
162 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); in pnv_dt_core()
167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); in pnv_dt_core()
173 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); in pnv_dt_core()
174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", in pnv_dt_core()
175 env->dcache_line_size))); in pnv_dt_core()
176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", in pnv_dt_core()
177 env->dcache_line_size))); in pnv_dt_core()
178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", in pnv_dt_core()
179 env->icache_line_size))); in pnv_dt_core()
180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", in pnv_dt_core()
181 env->icache_line_size))); in pnv_dt_core()
183 if (pcc->l1_dcache_size) { in pnv_dt_core()
184 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", in pnv_dt_core()
185 pcc->l1_dcache_size))); in pnv_dt_core()
189 if (pcc->l1_icache_size) { in pnv_dt_core()
190 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", in pnv_dt_core()
191 pcc->l1_icache_size))); in pnv_dt_core()
196 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); in pnv_dt_core()
197 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); in pnv_dt_core()
198 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", in pnv_dt_core()
199 cpu->hash64_opts->slb_size))); in pnv_dt_core()
201 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); in pnv_dt_core()
208 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", in pnv_dt_core()
218 if (env->insns_flags & PPC_ALTIVEC) { in pnv_dt_core()
219 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; in pnv_dt_core()
229 if (env->insns_flags2 & PPC2_DFP) { in pnv_dt_core()
236 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", in pnv_dt_core()
241 if (pc->big_core) { in pnv_dt_core()
244 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
247 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
250 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", in pnv_dt_core()
256 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
259 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", in pnv_dt_core()
274 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; in pnv_dt_icp()
279 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); in pnv_dt_icp()
293 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); in pnv_dt_icp()
301 "PowerPC-External-Interrupt-Presentation"))); in pnv_dt_icp()
302 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); in pnv_dt_icp()
303 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", in pnv_dt_icp()
305 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); in pnv_dt_icp()
306 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); in pnv_dt_icp()
318 phb->chip = chip; in pnv_chip_add_phb()
320 chip8->phbs[chip8->num_phbs] = phb; in pnv_chip_add_phb()
321 chip8->num_phbs++; in pnv_chip_add_phb()
338 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; in pnv_chip_power8_dt_populate()
346 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power8_dt_populate()
347 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate()
352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power8_dt_populate()
356 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); in pnv_chip_power8_dt_populate()
359 if (chip->ram_size) { in pnv_chip_power8_dt_populate()
360 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power8_dt_populate()
370 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
372 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
374 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
376 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
378 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
380 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
382 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
384 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
390 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
395 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; in pnv_chip_power9_dt_populate()
403 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power9_dt_populate()
404 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate()
409 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power9_dt_populate()
412 if (pnv_core->big_core) { in pnv_chip_power9_dt_populate()
413 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power9_dt_populate()
417 if (chip->ram_size) { in pnv_chip_power9_dt_populate()
418 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power9_dt_populate()
431 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
433 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
435 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
437 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
439 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
441 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
443 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
445 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
451 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
453 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
455 0x80, 0x00, /* 72 - 73 */
460 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; in pnv_chip_power10_dt_populate()
468 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power10_dt_populate()
469 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate()
474 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power10_dt_populate()
477 if (pnv_core->big_core) { in pnv_chip_power10_dt_populate()
478 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power10_dt_populate()
482 if (chip->ram_size) { in pnv_chip_power10_dt_populate()
483 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power10_dt_populate()
491 uint32_t io_base = d->ioport_id; in pnv_dt_rtc()
512 uint32_t io_base = d->ioport_id; in pnv_dt_serial()
533 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); in pnv_dt_serial()
534 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); in pnv_dt_serial()
536 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", in pnv_dt_serial()
545 const char compatible[] = "bt\0ipmi-bt"; in pnv_dt_ipmi_bt()
549 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ in pnv_dt_ipmi_bt()
573 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", in pnv_dt_ipmi_bt()
588 pnv_dt_rtc(d, args->fdt, args->offset); in pnv_dt_isa_device()
590 pnv_dt_serial(d, args->fdt, args->offset); in pnv_dt_isa_device()
591 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { in pnv_dt_isa_device()
592 pnv_dt_ipmi_bt(d, args->fdt, args->offset); in pnv_dt_isa_device()
595 d->ioport_id); in pnv_dt_isa_device()
607 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); in pnv_dt_isa()
624 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, in pnv_dt_isa()
633 off = fdt_add_subnode(fdt, off, "power-mgt"); in pnv_dt_power_mgt()
635 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); in pnv_dt_power_mgt()
654 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); in pnv_dt_create()
655 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); in pnv_dt_create()
658 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); in pnv_dt_create()
663 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); in pnv_dt_create()
668 if (machine->kernel_cmdline) { in pnv_dt_create()
670 machine->kernel_cmdline))); in pnv_dt_create()
673 if (pnv->initrd_size) { in pnv_dt_create()
674 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); in pnv_dt_create()
675 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); in pnv_dt_create()
677 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", in pnv_dt_create()
679 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", in pnv_dt_create()
684 for (i = 0; i < pnv->num_chips; i++) { in pnv_dt_create()
685 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); in pnv_dt_create()
691 if (pnv->bmc) { in pnv_dt_create()
692 pnv_dt_bmc_sensors(pnv->bmc, fdt); in pnv_dt_create()
696 if (pmc->dt_power_mgt) { in pnv_dt_create()
697 pmc->dt_power_mgt(pnv, fdt); in pnv_dt_create()
707 if (pnv->bmc) { in pnv_powerdown_notify()
708 pnv_bmc_powerdown(pnv->bmc); in pnv_powerdown_notify()
726 if (!pnv->bmc) { in pnv_reset()
729 warn_report("machine has no BMC device. Use '-device " in pnv_reset()
730 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " in pnv_reset()
734 pnv_bmc_set_pnor(bmc, pnv->pnor); in pnv_reset()
735 pnv->bmc = bmc; in pnv_reset()
739 if (machine->fdt) { in pnv_reset()
740 fdt = machine->fdt; in pnv_reset()
750 /* Update machine->fdt with latest fdt */ in pnv_reset()
751 if (machine->fdt != fdt) { in pnv_reset()
753 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free in pnv_reset()
754 * the existing machine->fdt to avoid leaking it during in pnv_reset()
757 g_free(machine->fdt); in pnv_reset()
758 machine->fdt = fdt; in pnv_reset()
765 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); in pnv_chip_power8_isa_create()
767 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); in pnv_chip_power8_isa_create()
769 return pnv_lpc_isa_create(&chip8->lpc, true, errp); in pnv_chip_power8_isa_create()
775 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); in pnv_chip_power8nvl_isa_create()
777 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); in pnv_chip_power8nvl_isa_create()
779 return pnv_lpc_isa_create(&chip8->lpc, false, errp); in pnv_chip_power8nvl_isa_create()
787 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); in pnv_chip_power9_isa_create()
788 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); in pnv_chip_power9_isa_create()
790 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); in pnv_chip_power9_isa_create()
791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); in pnv_chip_power9_isa_create()
792 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); in pnv_chip_power9_isa_create()
793 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); in pnv_chip_power9_isa_create()
794 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); in pnv_chip_power9_isa_create()
795 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); in pnv_chip_power9_isa_create()
796 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); in pnv_chip_power9_isa_create()
797 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); in pnv_chip_power9_isa_create()
799 return pnv_lpc_isa_create(&chip9->lpc, false, errp); in pnv_chip_power9_isa_create()
807 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); in pnv_chip_power10_isa_create()
808 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); in pnv_chip_power10_isa_create()
810 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); in pnv_chip_power10_isa_create()
811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); in pnv_chip_power10_isa_create()
812 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); in pnv_chip_power10_isa_create()
813 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); in pnv_chip_power10_isa_create()
814 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); in pnv_chip_power10_isa_create()
815 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); in pnv_chip_power10_isa_create()
816 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); in pnv_chip_power10_isa_create()
817 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); in pnv_chip_power10_isa_create()
819 return pnv_lpc_isa_create(&chip10->lpc, false, errp); in pnv_chip_power10_isa_create()
824 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); in pnv_isa_create()
832 ics_pic_print_info(&chip8->psi.ics, buf); in pnv_chip_power8_pic_print_info()
834 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_pic_print_info()
835 PnvPHB *phb = chip8->phbs[i]; in pnv_chip_power8_pic_print_info()
836 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_chip_power8_pic_print_info()
838 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); in pnv_chip_power8_pic_print_info()
839 ics_pic_print_info(&phb3->lsis, buf); in pnv_chip_power8_pic_print_info()
852 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); in pnv_chip_power9_pic_print_info_child()
861 pnv_xive_pic_print_info(&chip9->xive, buf); in pnv_chip_power9_pic_print_info()
862 pnv_psi_pic_print_info(&chip9->psi, buf); in pnv_chip_power9_pic_print_info()
892 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); in pnv_match_cpu()
897 ISADevice *dev = isa_new("isa-ipmi-bt"); in pnv_ipmi_bt_init()
908 pnv_xive2_pic_print_info(&chip10->xive, buf); in pnv_chip_power10_pic_print_info()
909 pnv_psi_pic_print_info(&chip10->psi, buf); in pnv_chip_power10_pic_print_info()
920 assert(machine->ram_size >= 1 * GiB); in pnv_chip_get_ram_size()
922 ram_per_chip = machine->ram_size / pnv->num_chips; in pnv_chip_get_ram_size()
927 assert(pnv->num_chips > 1); in pnv_chip_get_ram_size()
929 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); in pnv_chip_get_ram_size()
935 const char *bios_name = machine->firmware ?: FW_FILE_NAME; in pnv_init()
939 int max_smt_threads = pmc->max_smt_threads; in pnv_init()
950 mc->name); in pnv_init()
955 if (machine->ram_size < mc->default_ram_size) { in pnv_init()
956 char *sz = size_to_str(mc->default_ram_size); in pnv_init()
963 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { in pnv_init()
964 error_report("-append and -dtb cannot be used together, as passed" in pnv_init()
969 memory_region_add_subregion(get_system_memory(), 0, machine->ram); in pnv_init()
979 pnv->pnor = PNV_PNOR(dev); in pnv_init()
988 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); in pnv_init()
996 if (machine->kernel_filename) { in pnv_init()
999 kernel_size = load_image_targphys(machine->kernel_filename, in pnv_init()
1003 machine->kernel_filename); in pnv_init()
1009 if (machine->initrd_filename) { in pnv_init()
1010 pnv->initrd_base = INITRD_LOAD_ADDR; in pnv_init()
1011 pnv->initrd_size = load_image_targphys(machine->initrd_filename, in pnv_init()
1012 pnv->initrd_base, INITRD_MAX_SIZE); in pnv_init()
1013 if (pnv->initrd_size < 0) { in pnv_init()
1015 machine->initrd_filename); in pnv_init()
1021 if (machine->dtb) { in pnv_init()
1024 warn_report("with manually passed dtb, some options like '-append'" in pnv_init()
1025 " will get ignored and the dtb passed will be used as-is"); in pnv_init()
1027 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ in pnv_init()
1028 machine->fdt = load_device_tree(machine->dtb, &fdt_size); in pnv_init()
1029 if (!machine->fdt) { in pnv_init()
1030 error_report("Could not load dtb '%s'", machine->dtb); in pnv_init()
1042 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { in pnv_init()
1044 machine->cpu_type, mc->name); in pnv_init()
1049 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); in pnv_init()
1051 i, machine->cpu_type); in pnv_init()
1054 i, machine->cpu_type, mc->name); in pnv_init()
1058 /* Set lpar-per-core mode if lpar-per-thread is not supported */ in pnv_init()
1059 if (!pmc->has_lpar_per_thread) { in pnv_init()
1060 pnv->lpar_per_core = true; in pnv_init()
1063 pnv->num_chips = in pnv_init()
1064 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); in pnv_init()
1066 if (pnv->big_core) { in pnv_init()
1067 if (machine->smp.threads % 2 == 1) { in pnv_init()
1068 error_report("Cannot support %d threads with big-core option " in pnv_init()
1070 machine->smp.threads); in pnv_init()
1076 if (machine->smp.threads > max_smt_threads) { in pnv_init()
1078 "on %s machine", max_smt_threads, mc->desc); in pnv_init()
1079 if (pmc->max_smt_threads == 4) { in pnv_init()
1080 error_report("(use big-core=on for 8 threads per core)"); in pnv_init()
1085 if (pnv->big_core) { in pnv_init()
1087 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore in pnv_init()
1089 * device-tree and TCG SMT code make the 2 cores appear as one big core in pnv_init()
1093 machine->smp.cores *= 2; in pnv_init()
1094 machine->smp.threads /= 2; in pnv_init()
1097 if (!is_power_of_2(machine->smp.threads)) { in pnv_init()
1100 machine->smp.threads); in pnv_init()
1108 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { in pnv_init()
1109 error_report("invalid number of chips: '%d'", pnv->num_chips); in pnv_init()
1111 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); in pnv_init()
1115 pnv->chips = g_new0(PnvChip *, pnv->num_chips); in pnv_init()
1116 for (i = 0; i < pnv->num_chips; i++) { in pnv_init()
1121 pnv->chips[i] = PNV_CHIP(chip); in pnv_init()
1124 object_property_set_int(chip, "ram-start", chip_ram_start, in pnv_init()
1126 object_property_set_int(chip, "ram-size", chip_ram_size, in pnv_init()
1132 object_property_set_int(chip, "chip-id", i, &error_fatal); in pnv_init()
1133 object_property_set_int(chip, "nr-cores", machine->smp.cores, in pnv_init()
1135 object_property_set_int(chip, "nr-threads", machine->smp.threads, in pnv_init()
1137 object_property_set_bool(chip, "big-core", pnv->big_core, in pnv_init()
1139 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, in pnv_init()
1149 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), in pnv_init()
1157 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); in pnv_init()
1160 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); in pnv_init()
1163 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); in pnv_init()
1170 pnv->bmc = pnv_bmc_create(pnv->pnor); in pnv_init()
1171 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); in pnv_init()
1179 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, in pnv_init()
1180 &pnv->pnor->mmio); in pnv_init()
1186 pnv->powerdown_notifier.notify = pnv_powerdown_notify; in pnv_init()
1187 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); in pnv_init()
1190 * Create/Connect any machine-specific I2C devices in pnv_init()
1192 if (pmc->i2c_init) { in pnv_init()
1193 pmc->i2c_init(pnv); in pnv_init()
1198 * 0:21 Reserved - Read as zeros
1208 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p8()
1223 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); in pnv_chip_power8_intc_create()
1229 pnv_cpu->intc = obj; in pnv_chip_power8_intc_create()
1237 icp_reset(ICP(pnv_cpu->intc)); in pnv_chip_power8_intc_reset()
1244 icp_destroy(ICP(pnv_cpu->intc)); in pnv_chip_power8_intc_destroy()
1245 pnv_cpu->intc = NULL; in pnv_chip_power8_intc_destroy()
1251 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power8_intc_print_info()
1255 * 0:48 Reserved - Read as zeroes
1258 * 56 Reserved - Read as zero
1268 if (chip->big_core) { in pnv_get_pir_tir_p9()
1269 /* Big-core interleaves thread ID between small-cores */ in pnv_get_pir_tir_p9()
1275 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p9()
1279 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p9()
1288 * 0:48 Reserved - Read as zeroes
1291 * 56 Reserved - Read as zero
1294 * 61:63 Thread/Core Chiplet ID t0-t2
1302 if (chip->big_core) { in pnv_get_pir_tir_p10()
1303 /* Big-core interleaves thread ID between small-cores */ in pnv_get_pir_tir_p10()
1309 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p10()
1313 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p10()
1334 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), in pnv_chip_power9_intc_create()
1341 pnv_cpu->intc = obj; in pnv_chip_power9_intc_create()
1348 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power9_intc_reset()
1355 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power9_intc_destroy()
1356 pnv_cpu->intc = NULL; in pnv_chip_power9_intc_destroy()
1362 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power9_intc_print_info()
1378 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), in pnv_chip_power10_intc_create()
1385 pnv_cpu->intc = obj; in pnv_chip_power10_intc_create()
1392 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power10_intc_reset()
1399 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power10_intc_destroy()
1400 pnv_cpu->intc = NULL; in pnv_chip_power10_intc_destroy()
1406 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power10_intc_print_info()
1413 * EX1 - Venice only
1414 * EX2 - Venice only
1415 * EX3 - Venice only
1420 * EX9 - Venice only
1421 * EX10 - Venice only
1422 * EX11 - Venice only
1446 (Object **)&chip8->xics, in pnv_chip_power8_instance_init()
1450 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); in pnv_chip_power8_instance_init()
1452 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); in pnv_chip_power8_instance_init()
1454 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); in pnv_chip_power8_instance_init()
1456 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); in pnv_chip_power8_instance_init()
1459 chip8->num_phbs = pcc->num_phbs; in pnv_chip_power8_instance_init()
1461 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_instance_init()
1472 chip8->phbs[i] = PNV_PHB(phb); in pnv_chip_power8_instance_init()
1485 name = g_strdup_printf("icp-%x", chip->chip_id); in pnv_chip_icp_realize()
1486 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); in pnv_chip_icp_realize()
1489 &chip8->icp_mmio); in pnv_chip_icp_realize()
1492 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_icp_realize()
1493 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_icp_realize()
1494 int core_hwid = CPU_CORE(pnv_core)->core_id; in pnv_chip_icp_realize()
1496 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { in pnv_chip_icp_realize()
1500 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); in pnv_chip_icp_realize()
1501 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); in pnv_chip_icp_realize()
1503 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, in pnv_chip_icp_realize()
1504 &icp->mmio); in pnv_chip_icp_realize()
1514 Pnv8Psi *psi8 = &chip8->psi; in pnv_chip_power8_realize()
1518 assert(chip8->xics); in pnv_chip_power8_realize()
1523 pcc->parent_realize(dev, &local_err); in pnv_chip_power8_realize()
1533 OBJECT(chip8->xics), &error_abort); in pnv_chip_power8_realize()
1538 &PNV_PSI(psi8)->xscom_regs); in pnv_chip_power8_realize()
1541 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); in pnv_chip_power8_realize()
1542 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); in pnv_chip_power8_realize()
1544 chip->fw_mr = &chip8->lpc.isa_fw; in pnv_chip_power8_realize()
1545 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", in pnv_chip_power8_realize()
1560 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { in pnv_chip_power8_realize()
1563 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); in pnv_chip_power8_realize()
1564 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, in pnv_chip_power8_realize()
1569 &chip8->occ.sram_regs); in pnv_chip_power8_realize()
1572 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), in pnv_chip_power8_realize()
1574 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { in pnv_chip_power8_realize()
1578 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); in pnv_chip_power8_realize()
1582 &chip8->homer.regs); in pnv_chip_power8_realize()
1585 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_realize()
1586 PnvPHB *phb = chip8->phbs[i]; in pnv_chip_power8_realize()
1589 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, in pnv_chip_power8_realize()
1601 addr &= (PNV_XSCOM_SIZE - 1); in pnv_chip_power8_xscom_pcba()
1610 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ in pnv_chip_power8e_class_init()
1611 k->cores_mask = POWER8E_CORE_MASK; in pnv_chip_power8e_class_init()
1612 k->num_phbs = 3; in pnv_chip_power8e_class_init()
1613 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8e_class_init()
1614 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8e_class_init()
1615 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8e_class_init()
1616 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8e_class_init()
1617 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8e_class_init()
1618 k->isa_create = pnv_chip_power8_isa_create; in pnv_chip_power8e_class_init()
1619 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8e_class_init()
1620 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8e_class_init()
1621 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8e_class_init()
1622 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8e_class_init()
1623 dc->desc = "PowerNV Chip POWER8E"; in pnv_chip_power8e_class_init()
1626 &k->parent_realize); in pnv_chip_power8e_class_init()
1634 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ in pnv_chip_power8_class_init()
1635 k->cores_mask = POWER8_CORE_MASK; in pnv_chip_power8_class_init()
1636 k->num_phbs = 3; in pnv_chip_power8_class_init()
1637 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8_class_init()
1638 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8_class_init()
1639 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8_class_init()
1640 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8_class_init()
1641 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8_class_init()
1642 k->isa_create = pnv_chip_power8_isa_create; in pnv_chip_power8_class_init()
1643 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8_class_init()
1644 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8_class_init()
1645 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8_class_init()
1646 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8_class_init()
1647 dc->desc = "PowerNV Chip POWER8"; in pnv_chip_power8_class_init()
1650 &k->parent_realize); in pnv_chip_power8_class_init()
1658 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ in pnv_chip_power8nvl_class_init()
1659 k->cores_mask = POWER8_CORE_MASK; in pnv_chip_power8nvl_class_init()
1660 k->num_phbs = 4; in pnv_chip_power8nvl_class_init()
1661 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8nvl_class_init()
1662 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8nvl_class_init()
1663 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8nvl_class_init()
1664 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8nvl_class_init()
1665 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8nvl_class_init()
1666 k->isa_create = pnv_chip_power8nvl_isa_create; in pnv_chip_power8nvl_class_init()
1667 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8nvl_class_init()
1668 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8nvl_class_init()
1669 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8nvl_class_init()
1670 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8nvl_class_init()
1671 dc->desc = "PowerNV Chip POWER8NVL"; in pnv_chip_power8nvl_class_init()
1674 &k->parent_realize); in pnv_chip_power8nvl_class_init()
1684 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); in pnv_chip_power9_instance_init()
1685 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); in pnv_chip_power9_instance_init()
1686 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), in pnv_chip_power9_instance_init()
1687 "xive-fabric"); in pnv_chip_power9_instance_init()
1689 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); in pnv_chip_power9_instance_init()
1691 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); in pnv_chip_power9_instance_init()
1693 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); in pnv_chip_power9_instance_init()
1695 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); in pnv_chip_power9_instance_init()
1697 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); in pnv_chip_power9_instance_init()
1699 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); in pnv_chip_power9_instance_init()
1702 chip->num_pecs = pcc->num_pecs; in pnv_chip_power9_instance_init()
1704 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_instance_init()
1705 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], in pnv_chip_power9_instance_init()
1709 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power9_instance_init()
1710 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); in pnv_chip_power9_instance_init()
1719 int core_id = CPU_CORE(pnv_core)->core_id; in pnv_chip_quad_realize_one()
1726 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); in pnv_chip_quad_realize_one()
1735 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_quad_realize()
1736 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); in pnv_chip_quad_realize()
1738 for (i = 0; i < chip9->nr_quads; i++) { in pnv_chip_quad_realize()
1739 PnvQuad *eq = &chip9->quads[i]; in pnv_chip_quad_realize()
1741 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_quad_realize()
1744 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_quad_realize()
1745 &eq->xscom_regs); in pnv_chip_quad_realize()
1754 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_pec_realize()
1755 PnvPhb4PecState *pec = &chip9->pecs[i]; in pnv_chip_power9_pec_realize()
1761 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power9_pec_realize()
1769 pec_nest_base = pecc->xscom_nest_base(pec); in pnv_chip_power9_pec_realize()
1770 pec_pci_base = pecc->xscom_pci_base(pec); in pnv_chip_power9_pec_realize()
1772 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power9_pec_realize()
1773 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power9_pec_realize()
1782 Pnv9Psi *psi9 = &chip9->psi; in pnv_chip_power9_realize()
1789 pcc->parent_realize(dev, &local_err); in pnv_chip_power9_realize()
1796 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), in pnv_chip_power9_realize()
1798 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { in pnv_chip_power9_realize()
1802 &chip9->adu.xscom_regs); in pnv_chip_power9_realize()
1811 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", in pnv_chip_power9_realize()
1813 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", in pnv_chip_power9_realize()
1815 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", in pnv_chip_power9_realize()
1817 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", in pnv_chip_power9_realize()
1819 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1821 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { in pnv_chip_power9_realize()
1825 &chip9->xive.xscom_regs); in pnv_chip_power9_realize()
1837 &PNV_PSI(psi9)->xscom_regs); in pnv_chip_power9_realize()
1840 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { in pnv_chip_power9_realize()
1844 &chip9->lpc.xscom_regs); in pnv_chip_power9_realize()
1846 chip->fw_mr = &chip9->lpc.isa_fw; in pnv_chip_power9_realize()
1847 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power9_realize()
1851 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", in pnv_chip_power9_realize()
1852 chip->chip_id == 0, &error_abort); in pnv_chip_power9_realize()
1853 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", in pnv_chip_power9_realize()
1854 chip->chip_id == 1, &error_abort); in pnv_chip_power9_realize()
1855 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1857 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { in pnv_chip_power9_realize()
1861 &chip9->chiptod.xscom_regs); in pnv_chip_power9_realize()
1864 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { in pnv_chip_power9_realize()
1867 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); in pnv_chip_power9_realize()
1868 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( in pnv_chip_power9_realize()
1873 &chip9->occ.sram_regs); in pnv_chip_power9_realize()
1876 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { in pnv_chip_power9_realize()
1880 &chip9->sbe.xscom_ctrl_regs); in pnv_chip_power9_realize()
1882 &chip9->sbe.xscom_mbox_regs); in pnv_chip_power9_realize()
1883 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( in pnv_chip_power9_realize()
1887 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1889 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { in pnv_chip_power9_realize()
1893 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); in pnv_chip_power9_realize()
1897 &chip9->homer.regs); in pnv_chip_power9_realize()
1909 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power9_realize()
1910 Object *obj = OBJECT(&chip9->i2c[i]); in pnv_chip_power9_realize()
1913 object_property_set_int(obj, "num-busses", in pnv_chip_power9_realize()
1914 pcc->i2c_ports_per_engine[i], in pnv_chip_power9_realize()
1921 (chip9->i2c[i].engine - 1) * in pnv_chip_power9_realize()
1923 &chip9->i2c[i].xscom_regs); in pnv_chip_power9_realize()
1924 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, in pnv_chip_power9_realize()
1932 addr &= (PNV9_XSCOM_SIZE - 1); in pnv_chip_power9_xscom_pcba()
1942 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ in pnv_chip_power9_class_init()
1943 k->cores_mask = POWER9_CORE_MASK; in pnv_chip_power9_class_init()
1944 k->get_pir_tir = pnv_get_pir_tir_p9; in pnv_chip_power9_class_init()
1945 k->intc_create = pnv_chip_power9_intc_create; in pnv_chip_power9_class_init()
1946 k->intc_reset = pnv_chip_power9_intc_reset; in pnv_chip_power9_class_init()
1947 k->intc_destroy = pnv_chip_power9_intc_destroy; in pnv_chip_power9_class_init()
1948 k->intc_print_info = pnv_chip_power9_intc_print_info; in pnv_chip_power9_class_init()
1949 k->isa_create = pnv_chip_power9_isa_create; in pnv_chip_power9_class_init()
1950 k->dt_populate = pnv_chip_power9_dt_populate; in pnv_chip_power9_class_init()
1951 k->pic_print_info = pnv_chip_power9_pic_print_info; in pnv_chip_power9_class_init()
1952 k->xscom_core_base = pnv_chip_power9_xscom_core_base; in pnv_chip_power9_class_init()
1953 k->xscom_pcba = pnv_chip_power9_xscom_pcba; in pnv_chip_power9_class_init()
1954 dc->desc = "PowerNV Chip POWER9"; in pnv_chip_power9_class_init()
1955 k->num_pecs = PNV9_CHIP_MAX_PEC; in pnv_chip_power9_class_init()
1956 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; in pnv_chip_power9_class_init()
1957 k->i2c_ports_per_engine = i2c_ports_per_engine; in pnv_chip_power9_class_init()
1960 &k->parent_realize); in pnv_chip_power9_class_init()
1970 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); in pnv_chip_power10_instance_init()
1971 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); in pnv_chip_power10_instance_init()
1972 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), in pnv_chip_power10_instance_init()
1973 "xive-fabric"); in pnv_chip_power10_instance_init()
1974 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); in pnv_chip_power10_instance_init()
1975 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); in pnv_chip_power10_instance_init()
1976 object_initialize_child(obj, "chiptod", &chip10->chiptod, in pnv_chip_power10_instance_init()
1978 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); in pnv_chip_power10_instance_init()
1979 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); in pnv_chip_power10_instance_init()
1980 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); in pnv_chip_power10_instance_init()
1981 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, in pnv_chip_power10_instance_init()
1984 chip->num_pecs = pcc->num_pecs; in pnv_chip_power10_instance_init()
1986 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_instance_init()
1987 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], in pnv_chip_power10_instance_init()
1991 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power10_instance_init()
1992 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); in pnv_chip_power10_instance_init()
1996 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], in pnv_chip_power10_instance_init()
2006 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_power10_quad_realize()
2007 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); in pnv_chip_power10_quad_realize()
2009 for (i = 0; i < chip10->nr_quads; i++) { in pnv_chip_power10_quad_realize()
2010 PnvQuad *eq = &chip10->quads[i]; in pnv_chip_power10_quad_realize()
2012 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_power10_quad_realize()
2015 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2016 &eq->xscom_regs); in pnv_chip_power10_quad_realize()
2018 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2019 &eq->xscom_qme_regs); in pnv_chip_power10_quad_realize()
2028 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_phb_realize()
2029 PnvPhb4PecState *pec = &chip10->pecs[i]; in pnv_chip_power10_phb_realize()
2035 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power10_phb_realize()
2043 pec_nest_base = pecc->xscom_nest_base(pec); in pnv_chip_power10_phb_realize()
2044 pec_pci_base = pecc->xscom_pci_base(pec); in pnv_chip_power10_phb_realize()
2046 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power10_phb_realize()
2047 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power10_phb_realize()
2062 pcc->parent_realize(dev, &local_err); in pnv_chip_power10_realize()
2069 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), in pnv_chip_power10_realize()
2071 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { in pnv_chip_power10_realize()
2075 &chip10->adu.xscom_regs); in pnv_chip_power10_realize()
2084 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", in pnv_chip_power10_realize()
2086 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", in pnv_chip_power10_realize()
2088 object_property_set_int(OBJECT(&chip10->xive), "end-bar", in pnv_chip_power10_realize()
2090 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", in pnv_chip_power10_realize()
2092 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", in pnv_chip_power10_realize()
2094 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", in pnv_chip_power10_realize()
2096 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2098 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { in pnv_chip_power10_realize()
2102 &chip10->xive.xscom_regs); in pnv_chip_power10_realize()
2105 object_property_set_int(OBJECT(&chip10->psi), "bar", in pnv_chip_power10_realize()
2108 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, in pnv_chip_power10_realize()
2110 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { in pnv_chip_power10_realize()
2114 &PNV_PSI(&chip10->psi)->xscom_regs); in pnv_chip_power10_realize()
2117 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { in pnv_chip_power10_realize()
2121 &chip10->lpc.xscom_regs); in pnv_chip_power10_realize()
2123 chip->fw_mr = &chip10->lpc.isa_fw; in pnv_chip_power10_realize()
2124 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power10_realize()
2128 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", in pnv_chip_power10_realize()
2129 chip->chip_id == 0, &error_abort); in pnv_chip_power10_realize()
2130 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", in pnv_chip_power10_realize()
2131 chip->chip_id == 1, &error_abort); in pnv_chip_power10_realize()
2132 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2134 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { in pnv_chip_power10_realize()
2138 &chip10->chiptod.xscom_regs); in pnv_chip_power10_realize()
2141 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { in pnv_chip_power10_realize()
2145 &chip10->occ.xscom_regs); in pnv_chip_power10_realize()
2146 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( in pnv_chip_power10_realize()
2147 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); in pnv_chip_power10_realize()
2152 &chip10->occ.sram_regs); in pnv_chip_power10_realize()
2155 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { in pnv_chip_power10_realize()
2159 &chip10->sbe.xscom_ctrl_regs); in pnv_chip_power10_realize()
2161 &chip10->sbe.xscom_mbox_regs); in pnv_chip_power10_realize()
2162 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( in pnv_chip_power10_realize()
2163 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); in pnv_chip_power10_realize()
2166 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2168 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { in pnv_chip_power10_realize()
2173 &chip10->homer.pba_regs); in pnv_chip_power10_realize()
2177 &chip10->homer.regs); in pnv_chip_power10_realize()
2180 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { in pnv_chip_power10_realize()
2184 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); in pnv_chip_power10_realize()
2187 &chip10->n1_chiplet.xscom_pb_eq_mr); in pnv_chip_power10_realize()
2190 &chip10->n1_chiplet.xscom_pb_es_mr); in pnv_chip_power10_realize()
2203 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power10_realize()
2204 Object *obj = OBJECT(&chip10->i2c[i]); in pnv_chip_power10_realize()
2207 object_property_set_int(obj, "num-busses", in pnv_chip_power10_realize()
2208 pcc->i2c_ports_per_engine[i], in pnv_chip_power10_realize()
2215 (chip10->i2c[i].engine - 1) * in pnv_chip_power10_realize()
2217 &chip10->i2c[i].xscom_regs); in pnv_chip_power10_realize()
2218 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, in pnv_chip_power10_realize()
2219 qdev_get_gpio_in(DEVICE(&chip10->psi), in pnv_chip_power10_realize()
2224 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", in pnv_chip_power10_realize()
2227 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", in pnv_chip_power10_realize()
2230 (&chip10->pib_spic[i])), errp)) { in pnv_chip_power10_realize()
2235 &chip10->pib_spic[i].xscom_spic_regs); in pnv_chip_power10_realize()
2242 for (i = 0; i < pnv->num_chips; i++) { in pnv_rainier_i2c_init()
2243 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv_rainier_i2c_init()
2249 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], in pnv_rainier_i2c_init()
2253 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 in pnv_rainier_i2c_init()
2267 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); in pnv_rainier_i2c_init()
2273 addr &= (PNV10_XSCOM_SIZE - 1); in pnv_chip_power10_xscom_pcba()
2283 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ in pnv_chip_power10_class_init()
2284 k->cores_mask = POWER10_CORE_MASK; in pnv_chip_power10_class_init()
2285 k->get_pir_tir = pnv_get_pir_tir_p10; in pnv_chip_power10_class_init()
2286 k->intc_create = pnv_chip_power10_intc_create; in pnv_chip_power10_class_init()
2287 k->intc_reset = pnv_chip_power10_intc_reset; in pnv_chip_power10_class_init()
2288 k->intc_destroy = pnv_chip_power10_intc_destroy; in pnv_chip_power10_class_init()
2289 k->intc_print_info = pnv_chip_power10_intc_print_info; in pnv_chip_power10_class_init()
2290 k->isa_create = pnv_chip_power10_isa_create; in pnv_chip_power10_class_init()
2291 k->dt_populate = pnv_chip_power10_dt_populate; in pnv_chip_power10_class_init()
2292 k->pic_print_info = pnv_chip_power10_pic_print_info; in pnv_chip_power10_class_init()
2293 k->xscom_core_base = pnv_chip_power10_xscom_core_base; in pnv_chip_power10_class_init()
2294 k->xscom_pcba = pnv_chip_power10_xscom_pcba; in pnv_chip_power10_class_init()
2295 dc->desc = "PowerNV Chip POWER10"; in pnv_chip_power10_class_init()
2296 k->num_pecs = PNV10_CHIP_MAX_PEC; in pnv_chip_power10_class_init()
2297 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; in pnv_chip_power10_class_init()
2298 k->i2c_ports_per_engine = i2c_ports_per_engine; in pnv_chip_power10_class_init()
2301 &k->parent_realize); in pnv_chip_power10_class_init()
2314 if (!chip->cores_mask) { in pnv_chip_core_sanitize()
2315 chip->cores_mask = pcc->cores_mask; in pnv_chip_core_sanitize()
2319 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { in pnv_chip_core_sanitize()
2321 chip->cores_mask); in pnv_chip_core_sanitize()
2324 chip->cores_mask &= pcc->cores_mask; in pnv_chip_core_sanitize()
2326 /* Ensure small-cores a paired up in big-core mode */ in pnv_chip_core_sanitize()
2327 if (pnv->big_core) { in pnv_chip_core_sanitize()
2328 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; in pnv_chip_core_sanitize()
2329 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; in pnv_chip_core_sanitize()
2332 error_setg(errp, "warning: unpaired cores in big-core mode !"); in pnv_chip_core_sanitize()
2338 cores_max = ctpop64(chip->cores_mask); in pnv_chip_core_sanitize()
2339 if (chip->nr_cores > cores_max) { in pnv_chip_core_sanitize()
2367 chip->cores = g_new0(PnvCore *, chip->nr_cores); in pnv_chip_core_realize()
2369 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) in pnv_chip_core_realize()
2370 && (i < chip->nr_cores); core_hwid++) { in pnv_chip_core_realize()
2375 if (!(chip->cores_mask & (1ull << core_hwid))) { in pnv_chip_core_realize()
2383 chip->cores[i] = pnv_core; in pnv_chip_core_realize()
2384 object_property_set_int(OBJECT(pnv_core), "nr-threads", in pnv_chip_core_realize()
2385 chip->nr_threads, &error_fatal); in pnv_chip_core_realize()
2390 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, in pnv_chip_core_realize()
2392 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, in pnv_chip_core_realize()
2394 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", in pnv_chip_core_realize()
2395 pmc->quirk_tb_big_core, &error_fatal); in pnv_chip_core_realize()
2396 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", in pnv_chip_core_realize()
2397 chip->lpar_per_core, &error_fatal); in pnv_chip_core_realize()
2404 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); in pnv_chip_core_realize()
2407 &pnv_core->xscom_regs); in pnv_chip_core_realize()
2426 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2427 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2428 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2429 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2430 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2431 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2432 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
2433 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
2441 set_bit(DEVICE_CATEGORY_CPU, dc->categories); in pnv_chip_class_init()
2442 dc->realize = pnv_chip_realize; in pnv_chip_class_init()
2444 dc->desc = "PowerNV Chip"; in pnv_chip_class_init()
2451 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_core()
2452 PnvCore *pc = chip->cores[i]; in pnv_chip_find_core()
2455 if (cc->core_id == core_id) { in pnv_chip_find_core()
2466 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_cpu()
2467 PnvCore *pc = chip->cores[i]; in pnv_chip_find_cpu()
2470 for (j = 0; j < cc->nr_threads; j++) { in pnv_chip_find_cpu()
2471 if (ppc_cpu_pir(pc->threads[j]) == pir) { in pnv_chip_find_cpu()
2472 return pc->threads[j]; in pnv_chip_find_cpu()
2485 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_foreach_cpu()
2486 PnvCore *pc = chip->cores[i]; in pnv_chip_foreach_cpu()
2488 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { in pnv_chip_foreach_cpu()
2489 fn(chip, pc->threads[j], opaque); in pnv_chip_foreach_cpu()
2499 for (i = 0; i < pnv->num_chips; i++) { in pnv_ics_get()
2500 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); in pnv_ics_get()
2502 if (ics_valid_irq(&chip8->psi.ics, irq)) { in pnv_ics_get()
2503 return &chip8->psi.ics; in pnv_ics_get()
2506 for (j = 0; j < chip8->num_phbs; j++) { in pnv_ics_get()
2507 PnvPHB *phb = chip8->phbs[j]; in pnv_ics_get()
2508 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_ics_get()
2510 if (ics_valid_irq(&phb3->lsis, irq)) { in pnv_ics_get()
2511 return &phb3->lsis; in pnv_ics_get()
2514 if (ics_valid_irq(ICS(&phb3->msis), irq)) { in pnv_ics_get()
2515 return ICS(&phb3->msis); in pnv_ics_get()
2526 for (i = 0; i < pnv->num_chips; i++) { in pnv_get_chip()
2527 PnvChip *chip = pnv->chips[i]; in pnv_get_chip()
2528 if (chip->chip_id == chip_id) { in pnv_get_chip()
2540 for (i = 0; i < pnv->num_chips; i++) { in pnv_ics_resend()
2541 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); in pnv_ics_resend()
2543 ics_resend(&chip8->psi.ics); in pnv_ics_resend()
2545 for (j = 0; j < chip8->num_phbs; j++) { in pnv_ics_resend()
2546 PnvPHB *phb = chip8->phbs[j]; in pnv_ics_resend()
2547 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_ics_resend()
2549 ics_resend(&phb3->lsis); in pnv_ics_resend()
2550 ics_resend(ICS(&phb3->msis)); in pnv_ics_resend()
2559 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; in pnv_icp_get()
2565 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); in pnv_pic_intc_print_info()
2573 for (i = 0; i < pnv->num_chips; i++) { in pnv_pic_print_info()
2574 PnvChip *chip = pnv->chips[i]; in pnv_pic_print_info()
2580 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); in pnv_pic_print_info()
2594 for (i = 0; i < pnv->num_chips; i++) { in pnv_match_nvt()
2595 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); in pnv_match_nvt()
2596 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); in pnv_match_nvt()
2600 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, in pnv_match_nvt()
2623 for (i = 0; i < pnv->num_chips; i++) { in pnv10_xive_match_nvt()
2624 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv10_xive_match_nvt()
2625 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); in pnv10_xive_match_nvt()
2629 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, in pnv10_xive_match_nvt()
2645 return pnv->big_core; in pnv_machine_get_big_core()
2651 pnv->big_core = value; in pnv_machine_set_big_core()
2657 return pnv->lpar_per_core; in pnv_machine_get_lpar_per_core()
2663 pnv->lpar_per_core = value; in pnv_machine_set_lpar_per_core()
2670 return !!pnv->fw_load_addr; in pnv_machine_get_hb()
2678 pnv->fw_load_addr = 0x8000000; in pnv_machine_set_hb()
2694 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; in pnv_machine_power8_class_init()
2695 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); in pnv_machine_power8_class_init()
2696 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_power8_class_init()
2698 xic->icp_get = pnv_icp_get; in pnv_machine_power8_class_init()
2699 xic->ics_get = pnv_ics_get; in pnv_machine_power8_class_init()
2700 xic->ics_resend = pnv_ics_resend; in pnv_machine_power8_class_init()
2702 pmc->compat = compat; in pnv_machine_power8_class_init()
2703 pmc->compat_size = sizeof(compat); in pnv_machine_power8_class_init()
2704 pmc->max_smt_threads = 8; in pnv_machine_power8_class_init()
2705 /* POWER8 is always lpar-per-core mode */ in pnv_machine_power8_class_init()
2706 pmc->has_lpar_per_thread = false; in pnv_machine_power8_class_init()
2723 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; in pnv_machine_power9_class_init()
2724 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); in pnv_machine_power9_class_init()
2725 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_power9_class_init()
2727 xfc->match_nvt = pnv_match_nvt; in pnv_machine_power9_class_init()
2729 pmc->compat = compat; in pnv_machine_power9_class_init()
2730 pmc->compat_size = sizeof(compat); in pnv_machine_power9_class_init()
2731 pmc->max_smt_threads = 4; in pnv_machine_power9_class_init()
2732 pmc->has_lpar_per_thread = true; in pnv_machine_power9_class_init()
2733 pmc->dt_power_mgt = pnv_dt_power_mgt; in pnv_machine_power9_class_init()
2737 object_class_property_add_bool(oc, "big-core", in pnv_machine_power9_class_init()
2740 object_class_property_set_description(oc, "big-core", in pnv_machine_power9_class_init()
2741 "Use big-core (aka fused-core) mode"); in pnv_machine_power9_class_init()
2743 object_class_property_add_bool(oc, "lpar-per-core", in pnv_machine_power9_class_init()
2746 object_class_property_set_description(oc, "lpar-per-core", in pnv_machine_power9_class_init()
2762 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); in pnv_machine_p10_common_class_init()
2763 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_p10_common_class_init()
2765 mc->alias = "powernv"; in pnv_machine_p10_common_class_init()
2767 pmc->compat = compat; in pnv_machine_p10_common_class_init()
2768 pmc->compat_size = sizeof(compat); in pnv_machine_p10_common_class_init()
2769 pmc->max_smt_threads = 4; in pnv_machine_p10_common_class_init()
2770 pmc->has_lpar_per_thread = true; in pnv_machine_p10_common_class_init()
2771 pmc->quirk_tb_big_core = true; in pnv_machine_p10_common_class_init()
2772 pmc->dt_power_mgt = pnv_dt_power_mgt; in pnv_machine_p10_common_class_init()
2774 xfc->match_nvt = pnv10_xive_match_nvt; in pnv_machine_p10_common_class_init()
2784 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; in pnv_machine_power10_class_init()
2791 object_class_property_add_bool(oc, "big-core", in pnv_machine_power10_class_init()
2794 object_class_property_set_description(oc, "big-core", in pnv_machine_power10_class_init()
2795 "Use big-core (aka fused-core) mode"); in pnv_machine_power10_class_init()
2797 object_class_property_add_bool(oc, "lpar-per-core", in pnv_machine_power10_class_init()
2800 object_class_property_set_description(oc, "lpar-per-core", in pnv_machine_power10_class_init()
2810 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; in pnv_machine_p10_rainier_class_init()
2811 pmc->i2c_init = pnv_rainier_i2c_init; in pnv_machine_p10_rainier_class_init()
2820 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { in pnv_cpu_do_nmi_on_cpu()
2822 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the in pnv_cpu_do_nmi_on_cpu()
2826 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { in pnv_cpu_do_nmi_on_cpu()
2828 env->spr[SPR_SRR1] |= SRR1_WAKERESET; in pnv_cpu_do_nmi_on_cpu()
2832 * For non-powersave system resets, SRR1[42:45] are defined to be in pnv_cpu_do_nmi_on_cpu()
2833 * implementation-dependent. The POWER9 User Manual specifies that in pnv_cpu_do_nmi_on_cpu()
2838 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; in pnv_cpu_do_nmi_on_cpu()
2864 for (i = 0; i < pnv->num_chips; i++) { in pnv_nmi()
2865 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); in pnv_nmi()
2875 mc->desc = "IBM PowerNV (Non-Virtualized)"; in pnv_machine_class_init()
2876 mc->init = pnv_init; in pnv_machine_class_init()
2877 mc->reset = pnv_reset; in pnv_machine_class_init()
2878 mc->max_cpus = MAX_CPUS; in pnv_machine_class_init()
2879 /* Pnv provides a AHCI device for storage */ in pnv_machine_class_init()
2880 mc->block_default_type = IF_IDE; in pnv_machine_class_init()
2881 mc->no_parallel = 1; in pnv_machine_class_init()
2882 mc->default_boot_order = NULL; in pnv_machine_class_init()
2884 * RAM defaults to less than 2048 for 32-bit hosts, and large in pnv_machine_class_init()
2887 mc->default_ram_size = 1 * GiB; in pnv_machine_class_init()
2888 mc->default_ram_id = "pnv.ram"; in pnv_machine_class_init()
2889 ispc->print_info = pnv_pic_print_info; in pnv_machine_class_init()
2890 nc->nmi_monitor_handler = pnv_nmi; in pnv_machine_class_init()
2892 object_class_property_add_bool(oc, "hb-mode", in pnv_machine_class_init()
2894 object_class_property_set_description(oc, "hb-mode", in pnv_machine_class_init()
2921 .name = MACHINE_TYPE_NAME("powernv10-rainier"),