Lines Matching full:chip
96 * per chip.
114 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); in pnv_dt_memory()
139 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) in pnv_dt_core() argument
147 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); in pnv_dt_core()
161 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
171 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); in pnv_dt_core()
248 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
251 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
260 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
271 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, in pnv_dt_icp() argument
274 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_dt_icp()
283 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); in pnv_dt_icp()
284 addr = PNV_ICP_BASE(chip) | (pir << 12); in pnv_dt_icp()
315 * Adds a PnvPHB to the chip on P8.
318 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) in pnv_chip_add_phb() argument
320 Pnv8Chip *chip8 = PNV8_CHIP(chip); in pnv_chip_add_phb()
322 phb->chip = chip; in pnv_chip_add_phb()
326 return chip; in pnv_chip_add_phb()
340 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) in pnv_chip_power8_dt_populate() argument
345 pnv_dt_xscom(chip, fdt, 0, in pnv_chip_power8_dt_populate()
346 cpu_to_be64(PNV_XSCOM_BASE(chip)), in pnv_chip_power8_dt_populate()
350 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power8_dt_populate()
351 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate()
354 offset = pnv_dt_core(chip, pnv_core, fdt); in pnv_chip_power8_dt_populate()
360 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); in pnv_chip_power8_dt_populate()
363 if (chip->ram_size) { in pnv_chip_power8_dt_populate()
364 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power8_dt_populate()
397 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) in pnv_chip_power9_dt_populate() argument
402 pnv_dt_xscom(chip, fdt, 0, in pnv_chip_power9_dt_populate()
403 cpu_to_be64(PNV9_XSCOM_BASE(chip)), in pnv_chip_power9_dt_populate()
407 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power9_dt_populate()
408 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate()
411 offset = pnv_dt_core(chip, pnv_core, fdt); in pnv_chip_power9_dt_populate()
421 if (chip->ram_size) { in pnv_chip_power9_dt_populate()
422 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power9_dt_populate()
425 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); in pnv_chip_power9_dt_populate()
462 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) in pnv_chip_power10_dt_populate() argument
467 pnv_dt_xscom(chip, fdt, 0, in pnv_chip_power10_dt_populate()
468 cpu_to_be64(PNV10_XSCOM_BASE(chip)), in pnv_chip_power10_dt_populate()
472 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power10_dt_populate()
473 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate()
476 offset = pnv_dt_core(chip, pnv_core, fdt); in pnv_chip_power10_dt_populate()
486 if (chip->ram_size) { in pnv_chip_power10_dt_populate()
487 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power10_dt_populate()
490 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); in pnv_chip_power10_dt_populate()
606 * The default LPC bus of a multichip system is on chip 0. It's
687 /* Populate device tree for each chip */ in pnv_dt_create()
692 /* Populate ISA devices on chip 0 */ in pnv_dt_create()
765 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) in pnv_chip_power8_isa_create() argument
767 Pnv8Chip *chip8 = PNV8_CHIP(chip); in pnv_chip_power8_isa_create()
775 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) in pnv_chip_power8nvl_isa_create() argument
777 Pnv8Chip *chip8 = PNV8_CHIP(chip); in pnv_chip_power8nvl_isa_create()
785 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) in pnv_chip_power9_isa_create() argument
787 Pnv9Chip *chip9 = PNV9_CHIP(chip); in pnv_chip_power9_isa_create()
805 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) in pnv_chip_power10_isa_create() argument
807 Pnv10Chip *chip10 = PNV10_CHIP(chip); in pnv_chip_power10_isa_create()
825 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) in pnv_isa_create() argument
827 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); in pnv_isa_create()
830 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) in pnv_chip_power8_pic_print_info() argument
832 Pnv8Chip *chip8 = PNV8_CHIP(chip); in pnv_chip_power8_pic_print_info()
860 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) in pnv_chip_power9_pic_print_info() argument
862 Pnv9Chip *chip9 = PNV9_CHIP(chip); in pnv_chip_power9_pic_print_info()
866 object_child_foreach_recursive(OBJECT(chip), in pnv_chip_power9_pic_print_info()
870 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, in pnv_chip_power8_xscom_core_base() argument
876 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, in pnv_chip_power9_xscom_core_base() argument
882 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, in pnv_chip_power10_xscom_core_base() argument
907 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) in pnv_chip_power10_pic_print_info() argument
909 Pnv10Chip *chip10 = PNV10_CHIP(chip); in pnv_chip_power10_pic_print_info()
913 object_child_foreach_recursive(OBJECT(chip), in pnv_chip_power10_pic_print_info()
917 /* Always give the first 1GB to chip 0 else we won't boot */
1068 error_report("invalid chip model '%.*s' for %s machine", in pnv_init()
1121 * on #cores and Venice vs. Murano vs. Naples chip type etc..., in pnv_init()
1133 Object *chip = OBJECT(qdev_new(chip_typename)); in pnv_init() local
1136 pnv->chips[i] = PNV_CHIP(chip); in pnv_init()
1139 object_property_set_int(chip, "ram-start", chip_ram_start, in pnv_init()
1141 object_property_set_int(chip, "ram-size", chip_ram_size, in pnv_init()
1145 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); in pnv_init()
1146 object_property_add_child(OBJECT(pnv), chip_name, chip); in pnv_init()
1147 object_property_set_int(chip, "chip-id", i, &error_fatal); in pnv_init()
1148 object_property_set_int(chip, "nr-cores", machine->smp.cores, in pnv_init()
1150 object_property_set_int(chip, "nr-threads", machine->smp.threads, in pnv_init()
1152 object_property_set_bool(chip, "big-core", pnv->big_core, in pnv_init()
1154 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, in pnv_init()
1158 * Propagate the XICS fabric to the chip and its controllers. in pnv_init()
1161 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); in pnv_init()
1164 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), in pnv_init()
1167 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); in pnv_init()
1171 /* Instantiate ISA bus on chip 0 */ in pnv_init()
1214 * 22:24 Chip ID
1218 static void pnv_get_pir_tir_p8(PnvChip *chip, in pnv_get_pir_tir_p8() argument
1223 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p8()
1230 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power8_intc_create() argument
1233 Pnv8Chip *chip8 = PNV8_CHIP(chip); in pnv_chip_power8_intc_create()
1248 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power8_intc_reset() argument
1255 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power8_intc_destroy() argument
1263 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power8_intc_print_info() argument
1272 * 53:55 Chip ID
1279 static void pnv_get_pir_tir_p9(PnvChip *chip, in pnv_get_pir_tir_p9() argument
1283 if (chip->big_core) { in pnv_get_pir_tir_p9()
1290 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p9()
1294 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p9()
1305 * 53:55 Chip ID
1313 static void pnv_get_pir_tir_p10(PnvChip *chip, in pnv_get_pir_tir_p10() argument
1317 if (chip->big_core) { in pnv_get_pir_tir_p10()
1324 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p10()
1328 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p10()
1336 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power9_intc_create() argument
1339 Pnv9Chip *chip9 = PNV9_CHIP(chip); in pnv_chip_power9_intc_create()
1359 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power9_intc_reset() argument
1366 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power9_intc_destroy() argument
1374 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power9_intc_print_info() argument
1380 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power10_intc_create() argument
1383 Pnv10Chip *chip10 = PNV10_CHIP(chip); in pnv_chip_power10_intc_create()
1403 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power10_intc_reset() argument
1410 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) in pnv_chip_power10_intc_destroy() argument
1418 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, in pnv_chip_power10_intc_print_info() argument
1425 * Allowed core identifiers on a POWER8 Processor Chip :
1480 * We need the chip to parent the PHB to allow the DT in pnv_chip_power8_instance_init()
1495 PnvChip *chip = PNV_CHIP(chip8); in pnv_chip_icp_realize() local
1496 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_chip_icp_realize()
1500 name = g_strdup_printf("icp-%x", chip->chip_id); in pnv_chip_icp_realize()
1501 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); in pnv_chip_icp_realize()
1503 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), in pnv_chip_icp_realize()
1507 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_icp_realize()
1508 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_icp_realize()
1515 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); in pnv_chip_icp_realize()
1527 PnvChip *chip = PNV_CHIP(dev); in pnv_chip_power8_realize() local
1536 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); in pnv_chip_power8_realize()
1545 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), in pnv_chip_power8_realize()
1552 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, in pnv_chip_power8_realize()
1557 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); in pnv_chip_power8_realize()
1559 chip->fw_mr = &chip8->lpc.isa_fw; in pnv_chip_power8_realize()
1560 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", in pnv_chip_power8_realize()
1561 (uint64_t) PNV_XSCOM_BASE(chip), in pnv_chip_power8_realize()
1575 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), in pnv_chip_power8_realize()
1581 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); in pnv_chip_power8_realize()
1592 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); in pnv_chip_power8_realize()
1597 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), in pnv_chip_power8_realize()
1605 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, in pnv_chip_power8_realize()
1607 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), in pnv_chip_power8_realize()
1615 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) in pnv_chip_power8_xscom_pcba() argument
1639 dc->desc = "PowerNV Chip POWER8E"; in pnv_chip_power8e_class_init()
1663 dc->desc = "PowerNV Chip POWER8"; in pnv_chip_power8_class_init()
1687 dc->desc = "PowerNV Chip POWER8NVL"; in pnv_chip_power8nvl_class_init()
1695 PnvChip *chip = PNV_CHIP(obj); in pnv_chip_power9_instance_init() local
1717 /* Number of PECs is the chip default */ in pnv_chip_power9_instance_init()
1718 chip->num_pecs = pcc->num_pecs; in pnv_chip_power9_instance_init()
1720 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_instance_init()
1730 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, in pnv_chip_quad_realize_one() argument
1738 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, in pnv_chip_quad_realize_one()
1748 PnvChip *chip = PNV_CHIP(chip9); in pnv_chip_quad_realize() local
1751 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_quad_realize()
1757 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_quad_realize()
1760 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_quad_realize()
1765 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) in pnv_chip_power9_pec_realize() argument
1767 Pnv9Chip *chip9 = PNV9_CHIP(chip); in pnv_chip_power9_pec_realize()
1770 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_pec_realize()
1778 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power9_pec_realize()
1780 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), in pnv_chip_power9_pec_realize()
1790 pnv_xscom_add_subregion(chip, pec_cplt_base, in pnv_chip_power9_pec_realize()
1792 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power9_pec_realize()
1793 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power9_pec_realize()
1801 PnvChip *chip = PNV_CHIP(dev); in pnv_chip_power9_realize() local
1807 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); in pnv_chip_power9_realize()
1821 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, in pnv_chip_power9_realize()
1832 PNV9_XIVE_IC_BASE(chip), &error_fatal); in pnv_chip_power9_realize()
1834 PNV9_XIVE_VC_BASE(chip), &error_fatal); in pnv_chip_power9_realize()
1836 PNV9_XIVE_PC_BASE(chip), &error_fatal); in pnv_chip_power9_realize()
1838 PNV9_XIVE_TM_BASE(chip), &error_fatal); in pnv_chip_power9_realize()
1839 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1844 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, in pnv_chip_power9_realize()
1848 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), in pnv_chip_power9_realize()
1856 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, in pnv_chip_power9_realize()
1863 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), in pnv_chip_power9_realize()
1866 chip->fw_mr = &chip9->lpc.isa_fw; in pnv_chip_power9_realize()
1867 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power9_realize()
1868 (uint64_t) PNV9_LPCM_BASE(chip)); in pnv_chip_power9_realize()
1872 chip->chip_id == 0, &error_abort); in pnv_chip_power9_realize()
1874 chip->chip_id == 1, &error_abort); in pnv_chip_power9_realize()
1875 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1880 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, in pnv_chip_power9_realize()
1887 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, in pnv_chip_power9_realize()
1889 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, in pnv_chip_power9_realize()
1895 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1901 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); in pnv_chip_power9_realize()
1912 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); in pnv_chip_power9_realize()
1917 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), in pnv_chip_power9_realize()
1921 pnv_chip_power9_pec_realize(chip, &local_err); in pnv_chip_power9_realize()
1937 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); in pnv_chip_power9_realize()
1941 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + in pnv_chip_power9_realize()
1951 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) in pnv_chip_power9_xscom_pcba() argument
1975 dc->desc = "PowerNV Chip POWER9"; in pnv_chip_power9_class_init()
1986 PnvChip *chip = PNV_CHIP(obj); in pnv_chip_power10_instance_init() local
2005 chip->num_pecs = pcc->num_pecs; in pnv_chip_power10_instance_init()
2007 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_instance_init()
2024 PnvChip *chip = PNV_CHIP(chip10); in pnv_chip_power10_quad_realize() local
2027 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_power10_quad_realize()
2033 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_power10_quad_realize()
2036 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2039 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2044 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) in pnv_chip_power10_phb_realize() argument
2046 Pnv10Chip *chip10 = PNV10_CHIP(chip); in pnv_chip_power10_phb_realize()
2049 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_phb_realize()
2057 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power10_phb_realize()
2059 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), in pnv_chip_power10_phb_realize()
2069 pnv_xscom_add_subregion(chip, pec_cplt_base, in pnv_chip_power10_phb_realize()
2071 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power10_phb_realize()
2072 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power10_phb_realize()
2079 PnvChip *chip = PNV_CHIP(dev); in pnv_chip_power10_realize() local
2085 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); in pnv_chip_power10_realize()
2099 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, in pnv_chip_power10_realize()
2110 PNV10_XIVE2_IC_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2112 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2114 PNV10_XIVE2_END_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2116 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2118 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2120 PNV10_XIVE2_TM_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2121 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2126 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, in pnv_chip_power10_realize()
2131 PNV10_PSIHB_BASE(chip), &error_fatal); in pnv_chip_power10_realize()
2138 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, in pnv_chip_power10_realize()
2145 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), in pnv_chip_power10_realize()
2148 chip->fw_mr = &chip10->lpc.isa_fw; in pnv_chip_power10_realize()
2149 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power10_realize()
2150 (uint64_t) PNV10_LPCM_BASE(chip)); in pnv_chip_power10_realize()
2154 chip->chip_id == 0, &error_abort); in pnv_chip_power10_realize()
2156 chip->chip_id == 1, &error_abort); in pnv_chip_power10_realize()
2157 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2162 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, in pnv_chip_power10_realize()
2166 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2172 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, in pnv_chip_power10_realize()
2184 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, in pnv_chip_power10_realize()
2191 PNV10_OCC_SENSOR_BASE(chip), in pnv_chip_power10_realize()
2198 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, in pnv_chip_power10_realize()
2200 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, in pnv_chip_power10_realize()
2209 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, in pnv_chip_power10_realize()
2212 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, in pnv_chip_power10_realize()
2215 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, in pnv_chip_power10_realize()
2219 pnv_chip_power10_phb_realize(chip, &local_err); in pnv_chip_power10_realize()
2236 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); in pnv_chip_power10_realize()
2240 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + in pnv_chip_power10_realize()
2255 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id", in pnv_chip_power10_realize()
2256 chip->chip_id, &error_fatal); in pnv_chip_power10_realize()
2261 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + in pnv_chip_power10_realize()
2299 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) in pnv_chip_power10_xscom_pcba() argument
2323 dc->desc = "PowerNV Chip POWER10"; in pnv_chip_power10_class_init()
2332 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, in pnv_chip_core_sanitize() argument
2335 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_chip_core_sanitize()
2339 * No custom mask for this chip, let's use the default one from * in pnv_chip_core_sanitize()
2340 * the chip class in pnv_chip_core_sanitize()
2342 if (!chip->cores_mask) { in pnv_chip_core_sanitize()
2343 chip->cores_mask = pcc->cores_mask; in pnv_chip_core_sanitize()
2347 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { in pnv_chip_core_sanitize()
2348 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", in pnv_chip_core_sanitize()
2349 chip->cores_mask); in pnv_chip_core_sanitize()
2352 chip->cores_mask &= pcc->cores_mask; in pnv_chip_core_sanitize()
2356 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; in pnv_chip_core_sanitize()
2357 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; in pnv_chip_core_sanitize()
2366 cores_max = ctpop64(chip->cores_mask); in pnv_chip_core_sanitize()
2367 if (chip->nr_cores > cores_max) { in pnv_chip_core_sanitize()
2368 error_setg(errp, "warning: too many cores for chip ! Limit is %d", in pnv_chip_core_sanitize()
2374 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) in pnv_chip_core_realize() argument
2379 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_chip_core_realize()
2380 const char *typename = pnv_chip_core_typename(chip); in pnv_chip_core_realize()
2389 pnv_chip_core_sanitize(pnv, chip, &error); in pnv_chip_core_realize()
2395 chip->cores = g_new0(PnvCore *, chip->nr_cores); in pnv_chip_core_realize()
2397 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) in pnv_chip_core_realize()
2398 && (i < chip->nr_cores); core_hwid++) { in pnv_chip_core_realize()
2403 if (!(chip->cores_mask & (1ull << core_hwid))) { in pnv_chip_core_realize()
2410 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); in pnv_chip_core_realize()
2411 chip->cores[i] = pnv_core; in pnv_chip_core_realize()
2413 chip->nr_threads, &error_fatal); in pnv_chip_core_realize()
2420 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, in pnv_chip_core_realize()
2425 chip->lpar_per_core, &error_fatal); in pnv_chip_core_realize()
2426 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), in pnv_chip_core_realize()
2432 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); in pnv_chip_core_realize()
2434 pnv_xscom_add_subregion(chip, xscom_core_base, in pnv_chip_core_realize()
2442 PnvChip *chip = PNV_CHIP(dev); in pnv_chip_realize() local
2446 pnv_chip_core_realize(chip, &error); in pnv_chip_realize()
2454 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2471 dc->desc = "PowerNV Chip"; in pnv_chip_class_init()
2474 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) in pnv_chip_find_core() argument
2478 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_core()
2479 PnvCore *pc = chip->cores[i]; in pnv_chip_find_core()
2489 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) in pnv_chip_find_cpu() argument
2493 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_cpu()
2494 PnvCore *pc = chip->cores[i]; in pnv_chip_find_cpu()
2506 static void pnv_chip_foreach_cpu(PnvChip *chip, in pnv_chip_foreach_cpu() argument
2507 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), in pnv_chip_foreach_cpu() argument
2512 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_foreach_cpu()
2513 PnvCore *pc = chip->cores[i]; in pnv_chip_foreach_cpu()
2516 fn(chip, pc->threads[j], opaque); in pnv_chip_foreach_cpu()
2554 PnvChip *chip = pnv->chips[i]; in pnv_get_chip() local
2555 if (chip->chip_id == chip_id) { in pnv_get_chip()
2556 return chip; in pnv_get_chip()
2589 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, in pnv_pic_intc_print_info() argument
2592 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); in pnv_pic_intc_print_info()
2601 PnvChip *chip = pnv->chips[i]; in pnv_pic_print_info() local
2604 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); in pnv_pic_print_info()
2607 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); in pnv_pic_print_info()
2885 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) in pnv_cpu_do_nmi() argument
3006 * P10 chip and variants
3017 * P9 chip and variants
3028 * P8 chip and variants