Lines Matching +full:d +full:- +full:bus
2 * QEMU PCI bus manager
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
35 #include "migration/qemu-file-types.h"
42 #include "qemu/error-report.h"
51 #include "pci-internal.h"
84 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
90 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
92 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
96 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0),
97 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present,
99 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present,
101 DEFINE_PROP_SIZE32("x-max-bounce-buffer-size", PCIDevice,
103 DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present,
124 return a - b; in g_cmp_uint32()
141 memory_region_init_alias(&pci_dev->bus_master_enable_region, in pci_init_bus_master()
142 OBJECT(pci_dev), "bus master", in pci_init_bus_master()
143 dma_as->root, 0, memory_region_size(dma_as->root)); in pci_init_bus_master()
144 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); in pci_init_bus_master()
145 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, in pci_init_bus_master()
146 &pci_dev->bus_master_enable_region); in pci_init_bus_master()
151 PCIBus *bus = container_of(notifier, PCIBus, machine_done); in pcibus_machine_done() local
154 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pcibus_machine_done()
155 if (bus->devices[i]) { in pcibus_machine_done()
156 pci_init_bus_master(bus->devices[i]); in pcibus_machine_done()
163 PCIBus *bus = PCI_BUS(qbus); in pci_bus_realize() local
165 bus->machine_done.notify = pcibus_machine_done; in pci_bus_realize()
166 qemu_add_machine_init_done_notifier(&bus->machine_done); in pci_bus_realize()
168 vmstate_register_any(NULL, &vmstate_pcibus, bus); in pci_bus_realize()
173 PCIBus *bus = PCI_BUS(qbus); in pcie_bus_realize() local
183 * A PCI-E bus can support extended config space if it's the root in pcie_bus_realize()
184 * bus, or if the bus/bridge above it does as well in pcie_bus_realize()
186 if (pci_bus_is_root(bus)) { in pcie_bus_realize()
187 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in pcie_bus_realize()
189 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); in pcie_bus_realize()
192 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in pcie_bus_realize()
199 PCIBus *bus = PCI_BUS(qbus); in pci_bus_unrealize() local
201 qemu_remove_machine_init_done_notifier(&bus->machine_done); in pci_bus_unrealize()
203 vmstate_unregister(NULL, &vmstate_pcibus, bus); in pci_bus_unrealize()
206 static int pcibus_num(PCIBus *bus) in pcibus_num() argument
208 if (pci_bus_is_root(bus)) { in pcibus_num()
211 return bus->parent_dev->config[PCI_SECONDARY_BUS]; in pcibus_num()
214 static uint16_t pcibus_numa_node(PCIBus *bus) in pcibus_numa_node() argument
225 k->print_dev = pcibus_dev_print; in pci_bus_class_init()
226 k->get_dev_path = pcibus_get_dev_path; in pci_bus_class_init()
227 k->get_fw_dev_path = pcibus_get_fw_dev_path; in pci_bus_class_init()
228 k->realize = pci_bus_realize; in pci_bus_class_init()
229 k->unrealize = pci_bus_unrealize; in pci_bus_class_init()
231 rc->phases.hold = pcibus_reset_hold; in pci_bus_class_init()
233 pbc->bus_num = pcibus_num; in pci_bus_class_init()
234 pbc->numa_node = pcibus_numa_node; in pci_bus_class_init()
264 k->realize = pcie_bus_realize; in pcie_bus_class_init()
279 static void pci_update_mappings(PCIDevice *d);
289 int pci_bar(PCIDevice *d, int reg) in pci_bar() argument
294 assert(!pci_is_vf(d)); in pci_bar()
299 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_bar()
303 static inline int pci_irq_state(PCIDevice *d, int irq_num) in pci_irq_state() argument
305 return (d->irq_state >> irq_num) & 0x1; in pci_irq_state()
308 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) in pci_set_irq_state() argument
310 d->irq_state &= ~(0x1 << irq_num); in pci_set_irq_state()
311 d->irq_state |= level << irq_num; in pci_set_irq_state()
314 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) in pci_bus_change_irq_level() argument
317 assert(irq_num < bus->nirq); in pci_bus_change_irq_level()
318 bus->irq_count[irq_num] += change; in pci_bus_change_irq_level()
319 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); in pci_bus_change_irq_level()
324 PCIBus *bus; in pci_change_irq_level() local
327 bus = pci_get_bus(pci_dev); in pci_change_irq_level()
328 assert(bus->map_irq); in pci_change_irq_level()
329 irq_num = bus->map_irq(pci_dev, irq_num); in pci_change_irq_level()
330 trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num, in pci_change_irq_level()
331 pci_bus_is_root(bus) ? "root-complex" in pci_change_irq_level()
332 : DEVICE(bus->parent_dev)->canonical_path); in pci_change_irq_level()
333 if (bus->set_irq) in pci_change_irq_level()
335 pci_dev = bus->parent_dev; in pci_change_irq_level()
337 pci_bus_change_irq_level(bus, irq_num, change); in pci_change_irq_level()
340 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) in pci_bus_get_irq_level() argument
343 assert(irq_num < bus->nirq); in pci_bus_get_irq_level()
344 return !!bus->irq_count[irq_num]; in pci_bus_get_irq_level()
351 if (dev->irq_state) { in pci_update_irq_status()
352 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; in pci_update_irq_status()
354 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; in pci_update_irq_status()
382 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, in pci_msi_trigger()
394 PCIIORegion *region = &dev->io_regions[r]; in pci_reset_regions()
395 if (!region->size) { in pci_reset_regions()
399 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && in pci_reset_regions()
400 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { in pci_reset_regions()
401 pci_set_quad(dev->config + pci_bar(dev, r), region->type); in pci_reset_regions()
403 pci_set_long(dev->config + pci_bar(dev, r), region->type); in pci_reset_regions()
411 assert(dev->irq_state == 0); in pci_do_device_reset()
414 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, in pci_do_device_reset()
415 pci_get_word(dev->wmask + PCI_COMMAND) | in pci_do_device_reset()
416 pci_get_word(dev->w1cmask + PCI_COMMAND)); in pci_do_device_reset()
417 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, in pci_do_device_reset()
418 pci_get_word(dev->wmask + PCI_STATUS) | in pci_do_device_reset()
419 pci_get_word(dev->w1cmask + PCI_STATUS)); in pci_do_device_reset()
421 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, in pci_do_device_reset()
422 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | in pci_do_device_reset()
423 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); in pci_do_device_reset()
424 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; in pci_do_device_reset()
439 device_cold_reset(&dev->qdev); in pci_device_reset()
444 * Trigger pci bus reset under a given bus.
446 * have been reset device_cold_reset-ed already.
450 PCIBus *bus = PCI_BUS(obj); in pcibus_reset_hold() local
453 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pcibus_reset_hold()
454 if (bus->devices[i]) { in pcibus_reset_hold()
455 pci_do_device_reset(bus->devices[i]); in pcibus_reset_hold()
459 for (i = 0; i < bus->nirq; i++) { in pcibus_reset_hold()
460 assert(bus->irq_count[i] == 0); in pcibus_reset_hold()
478 PCIBus *pci_device_root_bus(const PCIDevice *d) in pci_device_root_bus() argument
480 PCIBus *bus = pci_get_bus(d); in pci_device_root_bus() local
482 while (!pci_bus_is_root(bus)) { in pci_device_root_bus()
483 d = bus->parent_dev; in pci_device_root_bus()
484 assert(d != NULL); in pci_device_root_bus()
486 bus = pci_get_bus(d); in pci_device_root_bus()
489 return bus; in pci_device_root_bus()
495 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); in pci_root_bus_path()
498 assert(host_bridge->bus == rootbus); in pci_root_bus_path()
500 if (hc->root_bus_path) { in pci_root_bus_path()
501 return (*hc->root_bus_path)(host_bridge, rootbus); in pci_root_bus_path()
504 return rootbus->qbus.name; in pci_root_bus_path()
507 bool pci_bus_bypass_iommu(PCIBus *bus) in pci_bus_bypass_iommu() argument
509 PCIBus *rootbus = bus; in pci_bus_bypass_iommu()
512 if (!pci_bus_is_root(bus)) { in pci_bus_bypass_iommu()
513 rootbus = pci_device_root_bus(bus->parent_dev); in pci_bus_bypass_iommu()
516 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); in pci_bus_bypass_iommu()
518 assert(host_bridge->bus == rootbus); in pci_bus_bypass_iommu()
520 return host_bridge->bypass_iommu; in pci_bus_bypass_iommu()
523 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, in pci_root_bus_internal_init() argument
528 bus->devfn_min = devfn_min; in pci_root_bus_internal_init()
529 bus->slot_reserved_mask = 0x0; in pci_root_bus_internal_init()
530 bus->address_space_mem = mem; in pci_root_bus_internal_init()
531 bus->address_space_io = io; in pci_root_bus_internal_init()
532 bus->flags |= PCI_BUS_IS_ROOT; in pci_root_bus_internal_init()
535 QLIST_INIT(&bus->child); in pci_root_bus_internal_init()
540 static void pci_bus_uninit(PCIBus *bus) in pci_bus_uninit() argument
542 pci_host_bus_unregister(BUS(bus)->parent); in pci_bus_uninit()
545 bool pci_bus_is_express(const PCIBus *bus) in pci_bus_is_express() argument
547 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); in pci_bus_is_express()
550 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, in pci_root_bus_init() argument
555 qbus_init(bus, bus_size, typename, parent, name); in pci_root_bus_init()
556 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); in pci_root_bus_init()
563 PCIBus *bus; in pci_root_bus_new() local
565 bus = PCI_BUS(qbus_new(typename, parent, name)); in pci_root_bus_new()
566 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); in pci_root_bus_new()
567 return bus; in pci_root_bus_new()
570 void pci_root_bus_cleanup(PCIBus *bus) in pci_root_bus_cleanup() argument
572 pci_bus_uninit(bus); in pci_root_bus_cleanup()
574 qbus_unrealize(BUS(bus)); in pci_root_bus_cleanup()
577 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, in pci_bus_irqs() argument
580 bus->set_irq = set_irq; in pci_bus_irqs()
581 bus->irq_opaque = irq_opaque; in pci_bus_irqs()
582 bus->nirq = nirq; in pci_bus_irqs()
583 g_free(bus->irq_count); in pci_bus_irqs()
584 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); in pci_bus_irqs()
587 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq) in pci_bus_map_irqs() argument
589 bus->map_irq = map_irq; in pci_bus_map_irqs()
592 void pci_bus_irqs_cleanup(PCIBus *bus) in pci_bus_irqs_cleanup() argument
594 bus->set_irq = NULL; in pci_bus_irqs_cleanup()
595 bus->map_irq = NULL; in pci_bus_irqs_cleanup()
596 bus->irq_opaque = NULL; in pci_bus_irqs_cleanup()
597 bus->nirq = 0; in pci_bus_irqs_cleanup()
598 g_free(bus->irq_count); in pci_bus_irqs_cleanup()
599 bus->irq_count = NULL; in pci_bus_irqs_cleanup()
609 PCIBus *bus; in pci_register_root_bus() local
611 bus = pci_root_bus_new(parent, name, mem, io, devfn_min, typename); in pci_register_root_bus()
612 pci_bus_irqs(bus, set_irq, irq_opaque, nirq); in pci_register_root_bus()
613 pci_bus_map_irqs(bus, map_irq); in pci_register_root_bus()
614 return bus; in pci_register_root_bus()
617 void pci_unregister_root_bus(PCIBus *bus) in pci_unregister_root_bus() argument
619 pci_bus_irqs_cleanup(bus); in pci_unregister_root_bus()
620 pci_root_bus_cleanup(bus); in pci_unregister_root_bus()
625 return PCI_BUS_GET_CLASS(s)->bus_num(s); in pci_bus_num()
628 /* Returns the min and max bus numbers of a PCI bus hierarchy */
629 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) in pci_bus_range() argument
632 *min_bus = *max_bus = pci_bus_num(bus); in pci_bus_range()
634 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_bus_range()
635 PCIDevice *dev = bus->devices[i]; in pci_bus_range()
638 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); in pci_bus_range()
639 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); in pci_bus_range()
644 int pci_bus_numa_node(PCIBus *bus) in pci_bus_numa_node() argument
646 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); in pci_bus_numa_node()
661 if ((config[i] ^ s->config[i]) & in get_pci_config_device()
662 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { in get_pci_config_device()
665 i, config[i], s->config[i], in get_pci_config_device()
666 s->cmask[i], s->wmask[i], s->w1cmask[i]); in get_pci_config_device()
668 return -EINVAL; in get_pci_config_device()
671 memcpy(s->config, config, size); in get_pci_config_device()
678 memory_region_set_enabled(&s->bus_master_enable_region, in get_pci_config_device()
679 pci_get_word(s->config + PCI_COMMAND) in get_pci_config_device()
712 fprintf(stderr, "irq state %d: must be 0 or 1.\n", in get_pci_irq_state()
714 return -EINVAL; in get_pci_irq_state()
782 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; in pci_device_save()
791 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); in pci_device_load()
799 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, in pci_set_default_subsystem_id()
801 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, in pci_set_default_subsystem_id()
806 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
807 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
815 unsigned long dom = 0, bus = 0; in pci_parse_devaddr() local
822 return -1; in pci_parse_devaddr()
824 bus = val; in pci_parse_devaddr()
828 return -1; in pci_parse_devaddr()
830 dom = bus; in pci_parse_devaddr()
831 bus = val; in pci_parse_devaddr()
835 return -1; in pci_parse_devaddr()
843 return -1; in pci_parse_devaddr()
848 return -1; in pci_parse_devaddr()
854 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) in pci_parse_devaddr()
855 return -1; in pci_parse_devaddr()
858 return -1; in pci_parse_devaddr()
861 *busp = bus; in pci_parse_devaddr()
870 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); in pci_init_cmask()
871 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); in pci_init_cmask()
872 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; in pci_init_cmask()
873 dev->cmask[PCI_REVISION_ID] = 0xff; in pci_init_cmask()
874 dev->cmask[PCI_CLASS_PROG] = 0xff; in pci_init_cmask()
875 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); in pci_init_cmask()
876 dev->cmask[PCI_HEADER_TYPE] = 0xff; in pci_init_cmask()
877 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; in pci_init_cmask()
884 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; in pci_init_wmask()
885 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; in pci_init_wmask()
886 pci_set_word(dev->wmask + PCI_COMMAND, in pci_init_wmask()
889 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); in pci_init_wmask()
891 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, in pci_init_wmask()
892 config_size - PCI_CONFIG_HEADER_SIZE); in pci_init_wmask()
901 pci_set_word(dev->w1cmask + PCI_STATUS, in pci_init_w1cmask()
907 static void pci_init_mask_bridge(PCIDevice *d) in pci_init_mask_bridge() argument
911 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); in pci_init_mask_bridge()
914 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; in pci_init_mask_bridge()
915 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; in pci_init_mask_bridge()
916 pci_set_word(d->wmask + PCI_MEMORY_BASE, in pci_init_mask_bridge()
918 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, in pci_init_mask_bridge()
920 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
922 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
926 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); in pci_init_mask_bridge()
929 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; in pci_init_mask_bridge()
930 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; in pci_init_mask_bridge()
931 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
933 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
937 * TODO: Bridges default to 10-bit VGA decoding but we currently only in pci_init_mask_bridge()
938 * implement 16-bit decoding (no alias support). in pci_init_mask_bridge()
940 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, in pci_init_mask_bridge()
954 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, in pci_init_mask_bridge()
956 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; in pci_init_mask_bridge()
957 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; in pci_init_mask_bridge()
958 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
960 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
964 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) in pci_init_multifunction() argument
966 uint8_t slot = PCI_SLOT(dev->devfn); in pci_init_multifunction()
969 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { in pci_init_multifunction()
970 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_init_multifunction()
979 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { in pci_init_multifunction()
985 * - all functions must set the bit to 1. in pci_init_multifunction()
987 * - function 0 must set the bit, but the rest function (> 0) in pci_init_multifunction()
996 if (PCI_FUNC(dev->devfn)) { in pci_init_multifunction()
997 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; in pci_init_multifunction()
998 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { in pci_init_multifunction()
1001 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); in pci_init_multifunction()
1007 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { in pci_init_multifunction()
1012 if (bus->devices[PCI_DEVFN(slot, func)]) { in pci_init_multifunction()
1025 pci_dev->config = g_malloc0(config_size); in pci_config_alloc()
1026 pci_dev->cmask = g_malloc0(config_size); in pci_config_alloc()
1027 pci_dev->wmask = g_malloc0(config_size); in pci_config_alloc()
1028 pci_dev->w1cmask = g_malloc0(config_size); in pci_config_alloc()
1029 pci_dev->used = g_malloc0(config_size); in pci_config_alloc()
1034 g_free(pci_dev->config); in pci_config_free()
1035 g_free(pci_dev->cmask); in pci_config_free()
1036 g_free(pci_dev->wmask); in pci_config_free()
1037 g_free(pci_dev->w1cmask); in pci_config_free()
1038 g_free(pci_dev->used); in pci_config_free()
1043 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; in do_pci_unregister_device()
1049 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { in do_pci_unregister_device()
1050 memory_region_del_subregion(&pci_dev->bus_master_container_region, in do_pci_unregister_device()
1051 &pci_dev->bus_master_enable_region); in do_pci_unregister_device()
1053 address_space_destroy(&pci_dev->bus_master_as); in do_pci_unregister_device()
1062 switch (cache->type) { in pci_req_id_cache_extract()
1064 result = pci_get_bdf(cache->dev); in pci_req_id_cache_extract()
1067 bus_n = pci_dev_bus_num(cache->dev); in pci_req_id_cache_extract()
1071 error_report("Invalid PCI requester ID cache type: %d", in pci_req_id_cache_extract()
1072 cache->type); in pci_req_id_cache_extract()
1084 * legacy PCI devices and PCIe-to-PCI bridges.
1087 * bus number might change from time to time.
1099 parent = pci_get_bus(dev)->parent_dev; in pci_req_id_cache_get()
1102 /* When we pass through PCIe-to-PCI/PCIX bridges, we in pci_req_id_cache_get()
1103 * override the requester ID using secondary bus in pci_req_id_cache_get()
1105 * (pcie-to-pci bridge spec chap 2.3). */ in pci_req_id_cache_get()
1128 return pci_req_id_cache_extract(&dev->requester_id_cache); in pci_requester_id()
1131 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) in pci_bus_devfn_available() argument
1133 return !(bus->devices[devfn]); in pci_bus_devfn_available()
1136 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) in pci_bus_devfn_reserved() argument
1138 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); in pci_bus_devfn_reserved()
1141 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus) in pci_bus_get_slot_reserved_mask() argument
1143 return bus->slot_reserved_mask; in pci_bus_get_slot_reserved_mask()
1146 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask) in pci_bus_set_slot_reserved_mask() argument
1148 bus->slot_reserved_mask |= mask; in pci_bus_set_slot_reserved_mask()
1151 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask) in pci_bus_clear_slot_reserved_mask() argument
1153 bus->slot_reserved_mask &= ~mask; in pci_bus_clear_slot_reserved_mask()
1156 /* -1 for devfn means auto assign */
1162 PCIConfigReadFunc *config_read = pc->config_read; in do_pci_register_device()
1163 PCIConfigWriteFunc *config_write = pc->config_write; in do_pci_register_device()
1166 PCIBus *bus = pci_get_bus(pci_dev); in do_pci_register_device() local
1170 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { in do_pci_register_device()
1173 bus->parent_dev->name); in do_pci_register_device()
1178 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); in do_pci_register_device()
1180 if (pci_bus_devfn_available(bus, devfn) && in do_pci_register_device()
1181 !pci_bus_devfn_reserved(bus, devfn)) { in do_pci_register_device()
1189 } else if (pci_bus_devfn_reserved(bus, devfn)) { in do_pci_register_device()
1190 error_setg(errp, "PCI: slot %d function %d not available for %s," in do_pci_register_device()
1194 } else if (!pci_bus_devfn_available(bus, devfn)) { in do_pci_register_device()
1195 error_setg(errp, "PCI: slot %d function %d not available for %s," in do_pci_register_device()
1198 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); in do_pci_register_device()
1204 * exposes other non-zero functions. Hence we need to ensure that in do_pci_register_device()
1207 if (dev->hotplugged && !pci_is_vf(pci_dev) && in do_pci_register_device()
1209 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," in do_pci_register_device()
1211 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), in do_pci_register_device()
1212 pci_get_function_0(pci_dev)->name, in do_pci_register_device()
1218 pci_dev->devfn = devfn; in do_pci_register_device()
1219 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); in do_pci_register_device()
1220 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); in do_pci_register_device()
1222 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), in do_pci_register_device()
1223 "bus master container", UINT64_MAX); in do_pci_register_device()
1224 address_space_init(&pci_dev->bus_master_as, in do_pci_register_device()
1225 &pci_dev->bus_master_container_region, pci_dev->name); in do_pci_register_device()
1226 pci_dev->bus_master_as.max_bounce_buffer_size = in do_pci_register_device()
1227 pci_dev->max_bounce_buffer_size; in do_pci_register_device()
1232 pci_dev->irq_state = 0; in do_pci_register_device()
1235 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); in do_pci_register_device()
1236 pci_config_set_device_id(pci_dev->config, pc->device_id); in do_pci_register_device()
1237 pci_config_set_revision(pci_dev->config, pc->revision); in do_pci_register_device()
1238 pci_config_set_class(pci_dev->config, pc->class_id); in do_pci_register_device()
1241 if (pc->subsystem_vendor_id || pc->subsystem_id) { in do_pci_register_device()
1242 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, in do_pci_register_device()
1243 pc->subsystem_vendor_id); in do_pci_register_device()
1244 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, in do_pci_register_device()
1245 pc->subsystem_id); in do_pci_register_device()
1251 assert(!pc->subsystem_vendor_id); in do_pci_register_device()
1252 assert(!pc->subsystem_id); in do_pci_register_device()
1260 pci_init_multifunction(bus, pci_dev, &local_err); in do_pci_register_device()
1271 pci_dev->config_read = config_read; in do_pci_register_device()
1272 pci_dev->config_write = config_write; in do_pci_register_device()
1273 bus->devices[devfn] = pci_dev; in do_pci_register_device()
1274 pci_dev->version_id = 2; /* Current pci device vmstate version */ in do_pci_register_device()
1284 r = &pci_dev->io_regions[i]; in pci_unregister_io_regions()
1285 if (!r->size || r->addr == PCI_BAR_UNMAPPED) in pci_unregister_io_regions()
1287 memory_region_del_subregion(r->address_space, r->memory); in pci_unregister_io_regions()
1301 if (pc->exit) { in pci_qdev_unrealize()
1302 pc->exit(pci_dev); in pci_qdev_unrealize()
1308 pci_dev->msi_trigger = NULL; in pci_qdev_unrealize()
1311 * clean up acpi-index so it could reused by another device in pci_qdev_unrealize()
1313 if (pci_dev->acpi_index) { in pci_qdev_unrealize()
1317 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_unrealize()
1338 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_register_bar()
1341 r = &pci_dev->io_regions[region_num]; in pci_register_bar()
1342 r->addr = PCI_BAR_UNMAPPED; in pci_register_bar()
1343 r->size = size; in pci_register_bar()
1344 r->type = type; in pci_register_bar()
1345 r->memory = memory; in pci_register_bar()
1346 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO in pci_register_bar()
1347 ? pci_get_bus(pci_dev)->address_space_io in pci_register_bar()
1348 : pci_get_bus(pci_dev)->address_space_mem; in pci_register_bar()
1350 wmask = ~(size - 1); in pci_register_bar()
1357 pci_set_long(pci_dev->config + addr, type); in pci_register_bar()
1359 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && in pci_register_bar()
1360 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { in pci_register_bar()
1361 pci_set_quad(pci_dev->wmask + addr, wmask); in pci_register_bar()
1362 pci_set_quad(pci_dev->cmask + addr, ~0ULL); in pci_register_bar()
1364 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); in pci_register_bar()
1365 pci_set_long(pci_dev->cmask + addr, 0xffffffff); in pci_register_bar()
1373 if (!pci_dev->has_vga) { in pci_update_vga()
1377 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); in pci_update_vga()
1379 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], in pci_update_vga()
1381 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], in pci_update_vga()
1383 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], in pci_update_vga()
1390 PCIBus *bus = pci_get_bus(pci_dev); in pci_register_vga() local
1392 assert(!pci_dev->has_vga); in pci_register_vga()
1395 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; in pci_register_vga()
1396 memory_region_add_subregion_overlap(bus->address_space_mem, in pci_register_vga()
1400 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; in pci_register_vga()
1401 memory_region_add_subregion_overlap(bus->address_space_io, in pci_register_vga()
1405 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; in pci_register_vga()
1406 memory_region_add_subregion_overlap(bus->address_space_io, in pci_register_vga()
1408 pci_dev->has_vga = true; in pci_register_vga()
1415 PCIBus *bus = pci_get_bus(pci_dev); in pci_unregister_vga() local
1417 if (!pci_dev->has_vga) { in pci_unregister_vga()
1421 memory_region_del_subregion(bus->address_space_mem, in pci_unregister_vga()
1422 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); in pci_unregister_vga()
1423 memory_region_del_subregion(bus->address_space_io, in pci_unregister_vga()
1424 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); in pci_unregister_vga()
1425 memory_region_del_subregion(bus->address_space_io, in pci_unregister_vga()
1426 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); in pci_unregister_vga()
1427 pci_dev->has_vga = false; in pci_unregister_vga()
1432 return pci_dev->io_regions[region_num].addr; in pci_get_bar_addr()
1435 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, in pci_config_get_bar_addr() argument
1439 if (!pci_is_vf(d)) { in pci_config_get_bar_addr()
1440 int bar = pci_bar(d, reg); in pci_config_get_bar_addr()
1442 new_addr = pci_get_quad(d->config + bar); in pci_config_get_bar_addr()
1444 new_addr = pci_get_long(d->config + bar); in pci_config_get_bar_addr()
1447 PCIDevice *pf = d->exp.sriov_vf.pf; in pci_config_get_bar_addr()
1448 uint16_t sriov_cap = pf->exp.sriov_cap; in pci_config_get_bar_addr()
1451 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); in pci_config_get_bar_addr()
1453 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); in pci_config_get_bar_addr()
1454 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; in pci_config_get_bar_addr()
1457 new_addr = pci_get_quad(pf->config + bar); in pci_config_get_bar_addr()
1459 new_addr = pci_get_long(pf->config + bar); in pci_config_get_bar_addr()
1465 new_addr &= ~(size - 1); in pci_config_get_bar_addr()
1470 pcibus_t pci_bar_address(PCIDevice *d, in pci_bar_address() argument
1474 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); in pci_bar_address()
1476 bool allow_0_address = mc->pci_allow_0_address; in pci_bar_address()
1482 new_addr = pci_config_get_bar_addr(d, reg, type, size); in pci_bar_address()
1483 last_addr = new_addr + size - 1; in pci_bar_address()
1497 new_addr = pci_config_get_bar_addr(d, reg, type, size); in pci_bar_address()
1502 new_addr &= ~(size - 1); in pci_bar_address()
1503 last_addr = new_addr + size - 1; in pci_bar_address()
1535 static void pci_update_mappings(PCIDevice *d) in pci_update_mappings() argument
1542 r = &d->io_regions[i]; in pci_update_mappings()
1545 if (!r->size) in pci_update_mappings()
1548 new_addr = pci_bar_address(d, i, r->type, r->size); in pci_update_mappings()
1549 if (!d->has_power) { in pci_update_mappings()
1554 if (new_addr == r->addr) in pci_update_mappings()
1558 if (r->addr != PCI_BAR_UNMAPPED) { in pci_update_mappings()
1559 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), in pci_update_mappings()
1560 PCI_SLOT(d->devfn), in pci_update_mappings()
1561 PCI_FUNC(d->devfn), in pci_update_mappings()
1562 i, r->addr, r->size); in pci_update_mappings()
1563 memory_region_del_subregion(r->address_space, r->memory); in pci_update_mappings()
1565 r->addr = new_addr; in pci_update_mappings()
1566 if (r->addr != PCI_BAR_UNMAPPED) { in pci_update_mappings()
1567 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), in pci_update_mappings()
1568 PCI_SLOT(d->devfn), in pci_update_mappings()
1569 PCI_FUNC(d->devfn), in pci_update_mappings()
1570 i, r->addr, r->size); in pci_update_mappings()
1571 memory_region_add_subregion_overlap(r->address_space, in pci_update_mappings()
1572 r->addr, r->memory, 1); in pci_update_mappings()
1576 pci_update_vga(d); in pci_update_mappings()
1579 static inline int pci_irq_disabled(PCIDevice *d) in pci_irq_disabled() argument
1581 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; in pci_irq_disabled()
1587 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) in pci_update_irq_disabled() argument
1589 int i, disabled = pci_irq_disabled(d); in pci_update_irq_disabled()
1593 int state = pci_irq_state(d, i); in pci_update_irq_disabled()
1594 pci_change_irq_level(d, i, disabled ? -state : state); in pci_update_irq_disabled()
1598 uint32_t pci_default_read_config(PCIDevice *d, in pci_default_read_config() argument
1603 assert(address + len <= pci_config_size(d)); in pci_default_read_config()
1605 if (pci_is_express_downstream_port(d) && in pci_default_read_config()
1606 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { in pci_default_read_config()
1607 pcie_sync_bridge_lnk(d); in pci_default_read_config()
1609 memcpy(&val, d->config + address, len); in pci_default_read_config()
1613 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) in pci_default_write_config() argument
1615 int i, was_irq_disabled = pci_irq_disabled(d); in pci_default_write_config()
1618 assert(addr + l <= pci_config_size(d)); in pci_default_write_config()
1621 uint8_t wmask = d->wmask[addr + i]; in pci_default_write_config()
1622 uint8_t w1cmask = d->w1cmask[addr + i]; in pci_default_write_config()
1624 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); in pci_default_write_config()
1625 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ in pci_default_write_config()
1631 pci_update_mappings(d); in pci_default_write_config()
1634 pci_update_irq_disabled(d, was_irq_disabled); in pci_default_write_config()
1635 memory_region_set_enabled(&d->bus_master_enable_region, in pci_default_write_config()
1636 (pci_get_word(d->config + PCI_COMMAND) in pci_default_write_config()
1637 & PCI_COMMAND_MASTER) && d->has_power); in pci_default_write_config()
1640 msi_write_config(d, addr, val_in, l); in pci_default_write_config()
1641 msix_write_config(d, addr, val_in, l); in pci_default_write_config()
1642 pcie_sriov_config_write(d, addr, val_in, l); in pci_default_write_config()
1656 change = level - pci_irq_state(pci_dev, irq_num); in pci_irq_handler()
1682 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) in pci_bus_set_route_irq_fn() argument
1684 assert(pci_bus_is_root(bus)); in pci_bus_set_route_irq_fn()
1685 bus->route_intx_to_irq = route_intx_to_irq; in pci_bus_set_route_irq_fn()
1690 PCIBus *bus; in pci_device_route_intx_to_irq() local
1694 bus = pci_get_bus(dev); in pci_device_route_intx_to_irq()
1695 pin = bus->map_irq(dev, pin); in pci_device_route_intx_to_irq()
1696 trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin, in pci_device_route_intx_to_irq()
1697 pci_bus_is_root(bus) ? "root-complex" in pci_device_route_intx_to_irq()
1698 : DEVICE(bus->parent_dev)->canonical_path); in pci_device_route_intx_to_irq()
1699 dev = bus->parent_dev; in pci_device_route_intx_to_irq()
1702 if (!bus->route_intx_to_irq) { in pci_device_route_intx_to_irq()
1703 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", in pci_device_route_intx_to_irq()
1704 object_get_typename(OBJECT(bus->qbus.parent))); in pci_device_route_intx_to_irq()
1705 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; in pci_device_route_intx_to_irq()
1708 return bus->route_intx_to_irq(bus->irq_opaque, pin); in pci_device_route_intx_to_irq()
1713 return old->mode != new->mode || old->irq != new->irq; in pci_intx_route_changed()
1716 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) in pci_bus_fire_intx_routing_notifier() argument
1722 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_bus_fire_intx_routing_notifier()
1723 dev = bus->devices[i]; in pci_bus_fire_intx_routing_notifier()
1724 if (dev && dev->intx_routing_notifier) { in pci_bus_fire_intx_routing_notifier()
1725 dev->intx_routing_notifier(dev); in pci_bus_fire_intx_routing_notifier()
1729 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_bus_fire_intx_routing_notifier()
1737 dev->intx_routing_notifier = notifier; in pci_device_set_intx_routing_notifier()
1741 * PCI-to-PCI bridge specification
1742 * 9.1: Interrupt routing. Table 9-1
1745 * 2.2.8.1: INTx interrupt signaling - Rules
1747 * Table 2-20
1751 * 0-origin unlike PCI interrupt pin register.
1755 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); in pci_swizzle_map_irq_fn()
1773 { 0x0201, "Token Ring controller", "token-ring"},
1779 { 0x0302, "3D controller"},
1793 { 0x0604, "PCI bridge", "pci-bridge"},
1801 { 0x0800, "Interrupt controller", "interrupt-controller"},
1802 { 0x0801, "DMA controller", "dma-controller"},
1811 { 0x0c01, "Access bus controller", "access-bus"},
1814 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1819 void pci_for_each_device_under_bus_reverse(PCIBus *bus, in pci_for_each_device_under_bus_reverse() argument
1823 PCIDevice *d; in pci_for_each_device_under_bus_reverse() local
1826 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { in pci_for_each_device_under_bus_reverse()
1827 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; in pci_for_each_device_under_bus_reverse()
1828 if (d) { in pci_for_each_device_under_bus_reverse()
1829 fn(bus, d, opaque); in pci_for_each_device_under_bus_reverse()
1834 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, in pci_for_each_device_reverse() argument
1837 bus = pci_find_bus_nr(bus, bus_num); in pci_for_each_device_reverse()
1839 if (bus) { in pci_for_each_device_reverse()
1840 pci_for_each_device_under_bus_reverse(bus, fn, opaque); in pci_for_each_device_reverse()
1844 void pci_for_each_device_under_bus(PCIBus *bus, in pci_for_each_device_under_bus() argument
1847 PCIDevice *d; in pci_for_each_device_under_bus() local
1850 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { in pci_for_each_device_under_bus()
1851 d = bus->devices[devfn]; in pci_for_each_device_under_bus()
1852 if (d) { in pci_for_each_device_under_bus()
1853 fn(bus, d, opaque); in pci_for_each_device_under_bus()
1858 void pci_for_each_device(PCIBus *bus, int bus_num, in pci_for_each_device() argument
1861 bus = pci_find_bus_nr(bus, bus_num); in pci_for_each_device()
1863 if (bus) { in pci_for_each_device()
1864 pci_for_each_device_under_bus(bus, fn, opaque); in pci_for_each_device()
1873 while (desc->desc && class != desc->class) { in get_class_desc()
1880 void pci_init_nic_devices(PCIBus *bus, const char *default_model) in pci_init_nic_devices() argument
1882 qemu_create_nic_bus_devices(&bus->qbus, TYPE_PCI_DEVICE, default_model, in pci_init_nic_devices()
1883 "virtio", "virtio-net-pci"); in pci_init_nic_devices()
1893 PCIBus *bus; in pci_init_nic_in_slot() local
1906 error_report("No support for non-zero PCI domains"); in pci_init_nic_in_slot()
1912 bus = pci_find_bus_nr(rootbus, busnr); in pci_init_nic_in_slot()
1913 if (!bus) { in pci_init_nic_in_slot()
1920 qdev_set_nic_properties(&pci_dev->qdev, nd); in pci_init_nic_in_slot()
1921 pci_realize_and_unref(pci_dev, bus, &error_fatal); in pci_init_nic_in_slot()
1925 PCIDevice *pci_vga_init(PCIBus *bus) in pci_vga_init() argument
1930 return pci_create_simple(bus, -1, "cirrus-vga"); in pci_vga_init()
1932 return pci_create_simple(bus, -1, "qxl-vga"); in pci_vga_init()
1934 return pci_create_simple(bus, -1, "VGA"); in pci_vga_init()
1936 return pci_create_simple(bus, -1, "vmware-svga"); in pci_vga_init()
1938 return pci_create_simple(bus, -1, "virtio-vga"); in pci_vga_init()
1940 default: /* Other non-PCI types. Checking for unsupported types is already in pci_vga_init()
1946 /* Whether a given bus number is in range of the secondary
1947 * bus of the given bridge device. */
1950 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & in pci_secondary_bus_in_range()
1951 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && in pci_secondary_bus_in_range()
1952 dev->config[PCI_SECONDARY_BUS] <= bus_num && in pci_secondary_bus_in_range()
1953 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; in pci_secondary_bus_in_range()
1956 /* Whether a given bus number is in a range of a root bus */
1957 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) in pci_root_bus_in_range() argument
1961 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_root_bus_in_range()
1962 PCIDevice *dev = bus->devices[i]; in pci_root_bus_in_range()
1974 PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) in pci_find_bus_nr() argument
1978 if (!bus) { in pci_find_bus_nr()
1982 if (pci_bus_num(bus) == bus_num) { in pci_find_bus_nr()
1983 return bus; in pci_find_bus_nr()
1986 /* Consider all bus numbers in range for the host pci bridge. */ in pci_find_bus_nr()
1987 if (!pci_bus_is_root(bus) && in pci_find_bus_nr()
1988 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { in pci_find_bus_nr()
1992 /* try child bus */ in pci_find_bus_nr()
1993 for (; bus; bus = sec) { in pci_find_bus_nr()
1994 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_find_bus_nr()
1998 /* PXB buses assumed to be children of bus 0 */ in pci_find_bus_nr()
2004 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { in pci_find_bus_nr()
2014 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, in pci_for_each_bus_depth_first() argument
2020 if (!bus) { in pci_for_each_bus_depth_first()
2025 state = begin(bus, parent_state); in pci_for_each_bus_depth_first()
2030 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_for_each_bus_depth_first()
2035 end(bus, state); in pci_for_each_bus_depth_first()
2040 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) in pci_find_device() argument
2042 bus = pci_find_bus_nr(bus, bus_num); in pci_find_device()
2044 if (!bus) in pci_find_device()
2047 return bus->devices[devfn]; in pci_find_device()
2050 #define ONBOARD_INDEX_MAX (16 * 1024 - 1)
2062 * capped by systemd (see: udev-builtin-net_id.c) in pci_qdev_realize()
2064 * misconfigure QEMU and then wonder why acpi-index doesn't work in pci_qdev_realize()
2066 if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) { in pci_qdev_realize()
2067 error_setg(errp, "acpi-index should be less or equal to %u", in pci_qdev_realize()
2073 * make sure that acpi-index is unique across all present PCI devices in pci_qdev_realize()
2075 if (pci_dev->acpi_index) { in pci_qdev_realize()
2079 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_realize()
2081 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 in pci_qdev_realize()
2082 " already exist", pci_dev->acpi_index); in pci_qdev_realize()
2086 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_realize()
2090 if (pci_dev->romsize != UINT32_MAX && !is_power_of_2(pci_dev->romsize)) { in pci_qdev_realize()
2091 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); in pci_qdev_realize()
2100 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; in pci_qdev_realize()
2104 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; in pci_qdev_realize()
2109 pci_dev->devfn, errp); in pci_qdev_realize()
2113 if (pc->realize) { in pci_qdev_realize()
2114 pc->realize(pci_dev, &local_err); in pci_qdev_realize()
2124 * associate only Device 0 with the device attached to the bus in pci_qdev_realize()
2127 * With ARI, PCI_SLOT() can return non-zero value as the traditional in pci_qdev_realize()
2128 * 5-bit Device Number and 3-bit Function Number fields in its associated in pci_qdev_realize()
2130 * single 8-bit Function Number. Hence, ignore ARI capable devices. in pci_qdev_realize()
2135 PCI_SLOT(pci_dev->devfn)) { in pci_qdev_realize()
2136 warn_report("PCI: slot %d is not valid for %s," in pci_qdev_realize()
2138 PCI_SLOT(pci_dev->devfn), pci_dev->name); in pci_qdev_realize()
2141 if (pci_dev->failover_pair_id) { in pci_qdev_realize()
2144 "PCIExpress bus"); in pci_qdev_realize()
2148 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); in pci_qdev_realize()
2155 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) in pci_qdev_realize()
2156 || (PCI_FUNC(pci_dev->devfn) != 0)) { in pci_qdev_realize()
2162 qdev->allow_unplug_during_migration = true; in pci_qdev_realize()
2167 if (pci_dev->romfile == NULL && pc->romfile != NULL) { in pci_qdev_realize()
2168 pci_dev->romfile = g_strdup(pc->romfile); in pci_qdev_realize()
2181 pci_dev->msi_trigger = pci_msi_trigger; in pci_qdev_realize()
2205 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) in pci_realize_and_unref() argument
2207 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); in pci_realize_and_unref()
2210 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, in pci_create_simple_multifunction() argument
2214 pci_realize_and_unref(dev, bus, &error_fatal); in pci_create_simple_multifunction()
2218 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) in pci_create_simple() argument
2221 pci_realize_and_unref(dev, bus, &error_fatal); in pci_create_simple()
2230 if (pdev->used[i]) in pci_find_space()
2232 else if (i - offset + 1 == size) in pci_find_space()
2243 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) in pci_find_capability_list()
2246 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); in pci_find_capability_list()
2248 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) in pci_find_capability_list()
2260 if (!(pdev->used[offset])) { in pci_find_capability_at_offset()
2264 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); in pci_find_capability_at_offset()
2266 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); in pci_find_capability_at_offset()
2302 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); in pci_patch_ids()
2303 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); in pci_patch_ids()
2307 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, in pci_patch_ids()
2315 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); in pci_patch_ids()
2324 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); in pci_patch_ids()
2347 if (!pdev->romfile || !strlen(pdev->romfile)) { in pci_add_option_rom()
2351 if (!pdev->rom_bar) { in pci_add_option_rom()
2356 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); in pci_add_option_rom()
2359 * Hot-plugged devices can't use the option ROM in pci_add_option_rom()
2362 if (DEVICE(pdev)->hotplugged) { in pci_add_option_rom()
2363 error_setg(errp, "Hot-plugged device without ROM bar" in pci_add_option_rom()
2369 rom_add_vga(pdev->romfile); in pci_add_option_rom()
2371 rom_add_option(pdev->romfile, -1); in pci_add_option_rom()
2376 if (load_file || pdev->romsize == UINT32_MAX) { in pci_add_option_rom()
2377 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); in pci_add_option_rom()
2379 path = g_strdup(pdev->romfile); in pci_add_option_rom()
2384 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); in pci_add_option_rom()
2387 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); in pci_add_option_rom()
2392 pdev->romfile); in pci_add_option_rom()
2395 if (pdev->romsize != UINT_MAX) { in pci_add_option_rom()
2396 if (size > pdev->romsize) { in pci_add_option_rom()
2399 pdev->romfile, (uint32_t)size, pdev->romsize); in pci_add_option_rom()
2403 pdev->romsize = pow2ceil(size); in pci_add_option_rom()
2409 vmsd ? vmsd->name : object_get_typename(OBJECT(pdev))); in pci_add_option_rom()
2411 pdev->has_rom = true; in pci_add_option_rom()
2412 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, in pci_add_option_rom()
2416 void *ptr = memory_region_get_ram_ptr(&pdev->rom); in pci_add_option_rom()
2419 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); in pci_add_option_rom()
2429 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); in pci_add_option_rom()
2434 if (!pdev->has_rom) in pci_del_option_rom()
2437 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); in pci_del_option_rom()
2438 pdev->has_rom = false; in pci_del_option_rom()
2470 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in pci_add_capability()
2472 return -EINVAL; in pci_add_capability()
2477 config = pdev->config + offset; in pci_add_capability()
2479 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; in pci_add_capability()
2480 pdev->config[PCI_CAPABILITY_LIST] = offset; in pci_add_capability()
2481 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; in pci_add_capability()
2482 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); in pci_add_capability()
2483 /* Make capability read-only by default */ in pci_add_capability()
2484 memset(pdev->wmask + offset, 0, size); in pci_add_capability()
2486 memset(pdev->cmask + offset, 0xFF, size); in pci_add_capability()
2496 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; in pci_del_capability()
2498 memset(pdev->wmask + offset, 0xff, size); in pci_del_capability()
2499 memset(pdev->w1cmask + offset, 0, size); in pci_del_capability()
2500 /* Clear cmask as device-specific registers can't be checked */ in pci_del_capability()
2501 memset(pdev->cmask + offset, 0, size); in pci_del_capability()
2502 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); in pci_del_capability()
2504 if (!pdev->config[PCI_CAPABILITY_LIST]) in pci_del_capability()
2505 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; in pci_del_capability()
2515 PCIDevice *d = (PCIDevice *)dev; in pci_dev_fw_name() local
2518 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); in pci_dev_fw_name()
2520 while (desc->desc && in pci_dev_fw_name()
2521 (class & ~desc->fw_ign_bits) != in pci_dev_fw_name()
2522 (desc->class & ~desc->fw_ign_bits)) { in pci_dev_fw_name()
2526 if (desc->desc) { in pci_dev_fw_name()
2527 name = desc->fw_name; in pci_dev_fw_name()
2534 pci_get_word(d->config + PCI_VENDOR_ID), in pci_dev_fw_name()
2535 pci_get_word(d->config + PCI_DEVICE_ID)); in pci_dev_fw_name()
2543 PCIDevice *d = (PCIDevice *)dev; in pcibus_get_fw_dev_path() local
2545 int has_func = !!PCI_FUNC(d->devfn); in pcibus_get_fw_dev_path()
2549 PCI_SLOT(d->devfn), in pcibus_get_fw_dev_path()
2552 PCI_FUNC(d->devfn)); in pcibus_get_fw_dev_path()
2557 PCIDevice *d = container_of(dev, PCIDevice, qdev); in pcibus_get_dev_path() local
2562 * domain:Bus:Slot.Func for systems without nested PCI bridges. in pcibus_get_dev_path()
2568 int slot_len = sizeof slot - 1 /* For '\0' */; in pcibus_get_dev_path()
2573 root_bus_path = pci_root_bus_path(d); in pcibus_get_dev_path()
2578 for (t = d; t; t = pci_get_bus(t)->parent_dev) { in pcibus_get_dev_path()
2593 for (t = d; t; t = pci_get_bus(t)->parent_dev) { in pcibus_get_dev_path()
2594 p -= slot_len; in pcibus_get_dev_path()
2596 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); in pcibus_get_dev_path()
2604 static int pci_qdev_find_recursive(PCIBus *bus, in pci_qdev_find_recursive() argument
2607 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); in pci_qdev_find_recursive()
2609 return -ENODEV; in pci_qdev_find_recursive()
2617 return -EINVAL; in pci_qdev_find_recursive()
2623 int rc = -ENODEV; in pci_qdev_find_device()
2626 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); in pci_qdev_find_device()
2631 if (tmp != -ENODEV) { in pci_qdev_find_device()
2641 return pci_get_bus(dev)->address_space_mem; in pci_address_space()
2646 return pci_get_bus(dev)->address_space_io; in pci_address_space_io()
2653 k->realize = pci_qdev_realize; in pci_device_class_init()
2654 k->unrealize = pci_qdev_unrealize; in pci_device_class_init()
2655 k->bus_type = TYPE_PCI_BUS; in pci_device_class_init()
2658 klass, "x-max-bounce-buffer-size", in pci_device_class_init()
2677 * Get IOMMU root bus, aliased bus and devfn of a PCI device
2679 * IOMMU root bus is needed by all call sites to call into iommu_ops.
2681 * aliased_[bus|devfn] is allowed.
2694 PCIBus *bus = pci_get_bus(dev); in pci_device_get_iommu_bus_devfn() local
2695 PCIBus *iommu_bus = bus; in pci_device_get_iommu_bus_devfn()
2696 int devfn = dev->devfn; in pci_device_get_iommu_bus_devfn()
2698 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { in pci_device_get_iommu_bus_devfn()
2699 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); in pci_device_get_iommu_bus_devfn()
2705 * conventional PCI buses pre-date such concepts. Instead, the PCIe- in pci_device_get_iommu_bus_devfn()
2706 * to-PCI bridge creates and accepts transactions on behalf of down- in pci_device_get_iommu_bus_devfn()
2709 * depends on the format of the bridge devices. Proper PCIe-to-PCI in pci_device_get_iommu_bus_devfn()
2711 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, in pci_device_get_iommu_bus_devfn()
2712 * where the bridge uses the seconary bus as the bridge portion of the in pci_device_get_iommu_bus_devfn()
2714 * found on the root complex such as the dmi-to-pci-bridge, we follow in pci_device_get_iommu_bus_devfn()
2715 * the convention of typical bare-metal hardware, which uses the in pci_device_get_iommu_bus_devfn()
2723 PCIDevice *parent = iommu_bus->parent_dev; in pci_device_get_iommu_bus_devfn()
2728 bus = iommu_bus; in pci_device_get_iommu_bus_devfn()
2730 devfn = parent->devfn; in pci_device_get_iommu_bus_devfn()
2731 bus = parent_bus; in pci_device_get_iommu_bus_devfn()
2741 if (pci_bus_bypass_iommu(bus) || !iommu_bus->iommu_ops) { in pci_device_get_iommu_bus_devfn()
2748 *aliased_bus = bus; in pci_device_get_iommu_bus_devfn()
2758 PCIBus *bus; in pci_device_iommu_address_space() local
2762 pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); in pci_device_iommu_address_space()
2764 return iommu_bus->iommu_ops->get_address_space(bus, in pci_device_iommu_address_space()
2765 iommu_bus->iommu_opaque, devfn); in pci_device_iommu_address_space()
2779 if (iommu_bus && iommu_bus->iommu_ops->set_iommu_device) { in pci_device_set_iommu_device()
2780 hiod->aliased_bus = aliased_bus; in pci_device_set_iommu_device()
2781 hiod->aliased_devfn = aliased_devfn; in pci_device_set_iommu_device()
2782 return iommu_bus->iommu_ops->set_iommu_device(pci_get_bus(dev), in pci_device_set_iommu_device()
2783 iommu_bus->iommu_opaque, in pci_device_set_iommu_device()
2784 dev->devfn, hiod, errp); in pci_device_set_iommu_device()
2794 if (iommu_bus && iommu_bus->iommu_ops->unset_iommu_device) { in pci_device_unset_iommu_device()
2795 return iommu_bus->iommu_ops->unset_iommu_device(pci_get_bus(dev), in pci_device_unset_iommu_device()
2796 iommu_bus->iommu_opaque, in pci_device_unset_iommu_device()
2797 dev->devfn); in pci_device_unset_iommu_device()
2801 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque) in pci_setup_iommu() argument
2805 * useful callbacks for the bus. in pci_setup_iommu()
2808 assert(ops->get_address_space); in pci_setup_iommu()
2810 bus->iommu_ops = ops; in pci_setup_iommu()
2811 bus->iommu_opaque = opaque; in pci_setup_iommu()
2817 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); in pci_dev_get_w64()
2837 PCIIORegion *r = &dev->io_regions[i]; in pci_dev_get_w64()
2841 if (!r->size || in pci_dev_get_w64()
2842 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || in pci_dev_get_w64()
2843 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { in pci_dev_get_w64()
2847 lob = pci_bar_address(dev, i, r->type, r->size); in pci_dev_get_w64()
2848 upb = lob + r->size - 1; in pci_dev_get_w64()
2862 void pci_bus_get_w64_range(PCIBus *bus, Range *range) in pci_bus_get_w64_range() argument
2865 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); in pci_bus_get_w64_range()
2879 parent_dev->exp.exp_cap && in pcie_has_upstream_port()
2886 PCIBus *bus = pci_get_bus(pci_dev); in pci_get_function_0() local
2890 return bus->devices[0]; in pci_get_function_0()
2892 /* Other bus types might support multiple devices at slots 0-31 */ in pci_get_function_0()
2893 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; in pci_get_function_0()
2912 void pci_set_power(PCIDevice *d, bool state) in pci_set_power() argument
2914 if (d->has_power == state) { in pci_set_power()
2918 d->has_power = state; in pci_set_power()
2919 pci_update_mappings(d); in pci_set_power()
2920 memory_region_set_enabled(&d->bus_master_enable_region, in pci_set_power()
2921 (pci_get_word(d->config + PCI_COMMAND) in pci_set_power()
2922 & PCI_COMMAND_MASTER) && d->has_power); in pci_set_power()
2923 if (!d->has_power) { in pci_set_power()
2924 pci_device_reset(d); in pci_set_power()