Lines Matching full:pci
2 * QEMU PowerPC E500 embedded processors pci controller emulation
21 #include "hw/pci/pci_device.h"
22 #include "hw/pci/pci_host.h"
23 #include "hw/pci-host/ppce500.h"
128 PPCE500PCIState *pci = opaque; in pci_reg_read4() local
143 value = pci->pob[idx].potar; in pci_reg_read4()
146 value = pci->pob[idx].potear; in pci_reg_read4()
149 value = pci->pob[idx].powbar; in pci_reg_read4()
152 value = pci->pob[idx].powar; in pci_reg_read4()
165 value = pci->pib[idx].pitar; in pci_reg_read4()
168 value = pci->pib[idx].piwbar; in pci_reg_read4()
171 value = pci->pib[idx].piwbear; in pci_reg_read4()
174 value = pci->pib[idx].piwar; in pci_reg_read4()
182 value = pci->gasket_time; in pci_reg_read4()
195 static void e500_update_piw(PPCE500PCIState *pci, int idx) in e500_update_piw() argument
197 uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; in e500_update_piw()
198 uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; in e500_update_piw()
199 uint64_t war = pci->pib[idx].piwar; in e500_update_piw()
202 MemoryRegion *mem = &pci->pib[idx].mem; in e500_update_piw()
203 MemoryRegion *bm = &pci->bm; in e500_update_piw()
217 name = g_strdup_printf("PCI Inbound Window %d", idx); in e500_update_piw()
218 memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, in e500_update_piw()
223 pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", in e500_update_piw()
228 static void e500_update_pow(PPCE500PCIState *pci, int idx) in e500_update_pow() argument
230 uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; in e500_update_pow()
231 uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; in e500_update_pow()
232 uint64_t war = pci->pob[idx].powar; in e500_update_pow()
234 MemoryRegion *mem = &pci->pob[idx].mem; in e500_update_pow()
249 name = g_strdup_printf("PCI Outbound Window %d", idx); in e500_update_pow()
250 memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, in e500_update_pow()
255 pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", in e500_update_pow()
262 PPCE500PCIState *pci = opaque; in pci_reg_write4() local
279 pci->pob[idx].potar = value; in pci_reg_write4()
280 e500_update_pow(pci, idx); in pci_reg_write4()
283 pci->pob[idx].potear = value; in pci_reg_write4()
284 e500_update_pow(pci, idx); in pci_reg_write4()
287 pci->pob[idx].powbar = value; in pci_reg_write4()
288 e500_update_pow(pci, idx); in pci_reg_write4()
291 pci->pob[idx].powar = value; in pci_reg_write4()
292 e500_update_pow(pci, idx); in pci_reg_write4()
305 pci->pib[idx].pitar = value; in pci_reg_write4()
306 e500_update_piw(pci, idx); in pci_reg_write4()
309 pci->pib[idx].piwbar = value; in pci_reg_write4()
310 e500_update_piw(pci, idx); in pci_reg_write4()
313 pci->pib[idx].piwbear = value; in pci_reg_write4()
314 e500_update_piw(pci, idx); in pci_reg_write4()
317 pci->pib[idx].piwar = value; in pci_reg_write4()
318 e500_update_piw(pci, idx); in pci_reg_write4()
326 pci->gasket_time = value; in pci_reg_write4()
358 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); in mpc85xx_pci_set_irq()
371 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); in e500_route_intx_pin_to_irq()
423 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", in e500_pcihost_bridge_realize()
459 memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); in e500_pcihost_realize()
460 memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); in e500_pcihost_realize()
470 /* Set up PCI view of memory */ in e500_pcihost_realize()
473 address_space_init(&s->bm_as, &s->bm, "pci-bm"); in e500_pcihost_realize()
478 memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); in e500_pcihost_realize()
480 "pci-conf-idx", 4); in e500_pcihost_realize()
482 "pci-conf-data", 4); in e500_pcihost_realize()
484 "pci.reg", PCIE500_REG_SIZE); in e500_pcihost_realize()
503 * PCI-facing part of the host bridge, not usable without the in e500_host_bridge_class_init()