26 #define phb_error(phb, fmt, ...)                                        \  macro
136         phb_error(phb, "rc_config_write invalid size %d", size);  in pnv_phb4_rc_config_write()
142         phb_error(phb, "rc_config_write device not found");  in pnv_phb4_rc_config_write()
158         phb_error(phb, "rc_config_read invalid size %d", size);  in pnv_phb4_rc_config_read()
164         phb_error(phb, "rc_config_read device not found");  in pnv_phb4_rc_config_read()
203             phb_error(phb, "M32 set beyond 4GB boundary !");  in pnv_phb4_check_mbt()
224         phb_error(phb, "PHB MBAR %d out of parent bounds", index);  in pnv_phb4_check_mbt()
301         phb_error(phb, "invalid IODA table %d", table);  in pnv_phb4_ioda_access()
522         phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",  in pnv_phb4_reg_write()
657         phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",  in pnv_phb4_reg_read()
750             phb_error(phb, "Invalid indirect address");  in pnv_phb4_xscom_read()
802             phb_error(phb, "Invalid indirect address");  in pnv_phb4_xscom_write()
1174         phb_error(phb, "IRQ %x is not an LSI", irq_num);  in pnv_phb4_set_irq()
1196         phb_error(ds->phb, "DMA with RTT BAR disabled !");  in pnv_phb4_resolve_pe()
1207         phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr);  in pnv_phb4_resolve_pe()
1216         phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte);  in pnv_phb4_resolve_pe()
1234         phb_error(ds->phb, "Invalid #levels in TVE %d", lev);  in pnv_phb4_translate_tve()
1240         phb_error(ds->phb, "Access to invalid TVE");  in pnv_phb4_translate_tve()
1279                 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr);  in pnv_phb4_translate_tve()
1286                 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr);  in pnv_phb4_translate_tve()
1287                 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,  in pnv_phb4_translate_tve()
1289                 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",  in pnv_phb4_translate_tve()
1299             phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr);  in pnv_phb4_translate_tve()
1300             phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,  in pnv_phb4_translate_tve()
1302             phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",  in pnv_phb4_translate_tve()
1332         phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",  in pnv_phb4_translate_iommu()
1344             phb_error(ds->phb, "xlate on 32-bit MSI region");  in pnv_phb4_translate_iommu()
1353         phb_error(ds->phb, "xlate on 64-bit MSI region");  in pnv_phb4_translate_iommu()
1356         phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr);  in pnv_phb4_translate_iommu()
1410         phb_error(phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",  in pnv_phb4_msi_write()
1417         phb_error(phb, "MSI %d out of bounds", src);  in pnv_phb4_msi_write()
1431     phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr);  in pnv_phb4_msi_read()
1653         phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr);  in pnv_phb4_xive_notify_abt()
1675         phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", notif_port);  in pnv_phb4_xive_notify_ic()