131     DesignwarePCIEViewport *viewport =  in designware_pcie_root_config_read()  local
184         val = viewport->base;  in designware_pcie_root_config_read()
188         val = viewport->base >> 32;  in designware_pcie_root_config_read()
192         val = viewport->target;  in designware_pcie_root_config_read()
196         val = viewport->target >> 32;  in designware_pcie_root_config_read()
200         val = viewport->limit;  in designware_pcie_root_config_read()
205         val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /  in designware_pcie_root_config_read()
220     DesignwarePCIEViewport *viewport = opaque;  in designware_pcie_root_data_access()  local
221     DesignwarePCIERoot *root = viewport->root;  in designware_pcie_root_data_access()
223     const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);  in designware_pcie_root_data_access()
224     const uint8_t devfn  = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);  in designware_pcie_root_data_access()
268                                             DesignwarePCIEViewport *viewport)  in designware_pcie_update_viewport()  argument
270     const uint64_t target = viewport->target;  in designware_pcie_update_viewport()
271     const uint64_t base   = viewport->base;  in designware_pcie_update_viewport()
272     const uint64_t size   = (uint64_t)viewport->limit - base + 1;  in designware_pcie_update_viewport()
273     const bool enabled    = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;  in designware_pcie_update_viewport()
277     if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {  in designware_pcie_update_viewport()
278         current = &viewport->mem;  in designware_pcie_update_viewport()
279         other   = &viewport->cfg;  in designware_pcie_update_viewport()
282         current = &viewport->cfg;  in designware_pcie_update_viewport()
283         other   = &viewport->mem;  in designware_pcie_update_viewport()
304     DesignwarePCIEViewport *viewport =  in designware_pcie_root_config_write()  local
349         viewport->base &= 0xFFFFFFFF00000000ULL;  in designware_pcie_root_config_write()
350         viewport->base |= val;  in designware_pcie_root_config_write()
354         viewport->base &= 0x00000000FFFFFFFFULL;  in designware_pcie_root_config_write()
355         viewport->base |= (uint64_t)val << 32;  in designware_pcie_root_config_write()
359         viewport->target &= 0xFFFFFFFF00000000ULL;  in designware_pcie_root_config_write()
360         viewport->target |= val;  in designware_pcie_root_config_write()
364         viewport->target &= 0x00000000FFFFFFFFULL;  in designware_pcie_root_config_write()
365         viewport->target |= val;  in designware_pcie_root_config_write()
369         viewport->limit = val;  in designware_pcie_root_config_write()
373         viewport->cr[0] = val;  in designware_pcie_root_config_write()
376         viewport->cr[1] = val;  in designware_pcie_root_config_write()
377         designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_config_write()
400     DesignwarePCIEViewport *viewport;  in designware_pcie_root_realize()  local
430         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];  in designware_pcie_root_realize()
431         viewport->inbound = true;  in designware_pcie_root_realize()
432         viewport->base    = 0x0000000000000000ULL;  in designware_pcie_root_realize()
433         viewport->target  = 0x0000000000000000ULL;  in designware_pcie_root_realize()
434         viewport->limit   = UINT32_MAX;  in designware_pcie_root_realize()
435         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;  in designware_pcie_root_realize()
445         mem  = &viewport->mem;  in designware_pcie_root_realize()
453         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];  in designware_pcie_root_realize()
454         viewport->root    = root;  in designware_pcie_root_realize()
455         viewport->inbound = false;  in designware_pcie_root_realize()
456         viewport->base    = 0x0000000000000000ULL;  in designware_pcie_root_realize()
457         viewport->target  = 0x0000000000000000ULL;  in designware_pcie_root_realize()
458         viewport->limit   = UINT32_MAX;  in designware_pcie_root_realize()
459         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;  in designware_pcie_root_realize()
469         mem  = &viewport->mem;  in designware_pcie_root_realize()
481         mem  = &viewport->cfg;  in designware_pcie_root_realize()
483         memory_region_init_io(&viewport->cfg, OBJECT(root),  in designware_pcie_root_realize()
485                               viewport, name, dummy_size);  in designware_pcie_root_realize()
500     viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];  in designware_pcie_root_realize()
501     viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;  in designware_pcie_root_realize()
502     designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_realize()