61 designware_pcie_root_to_host(DesignwarePCIERoot *root)  in designware_pcie_root_to_host()  argument
63     BusState *bus = qdev_get_parent_bus(DEVICE(root));  in designware_pcie_root_to_host()
87     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);  in designware_pcie_root_msi_write()  local
88     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_msi_write()
90     root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;  in designware_pcie_root_msi_write()
92     if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {  in designware_pcie_root_msi_write()
107 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)  in designware_pcie_root_update_msi_mapping()  argument
110     MemoryRegion *mem   = &root->msi.iomem;  in designware_pcie_root_update_msi_mapping()
111     const uint64_t base = root->msi.base;  in designware_pcie_root_update_msi_mapping()
112     const bool enable   = root->msi.intr[0].enable;  in designware_pcie_root_update_msi_mapping()
119 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)  in designware_pcie_root_get_current_viewport()  argument
121     const unsigned int idx = root->atu_viewport & 0xF;  in designware_pcie_root_get_current_viewport()
123         !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);  in designware_pcie_root_get_current_viewport()
124     return &root->viewports[dir][idx];  in designware_pcie_root_get_current_viewport()
130     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);  in designware_pcie_root_config_read()  local
132         designware_pcie_root_get_current_viewport(root);  in designware_pcie_root_config_read()
156         val = root->msi.base;  in designware_pcie_root_config_read()
160         val = root->msi.base >> 32;  in designware_pcie_root_config_read()
164         val = root->msi.intr[0].enable;  in designware_pcie_root_config_read()
168         val = root->msi.intr[0].mask;  in designware_pcie_root_config_read()
172         val = root->msi.intr[0].status;  in designware_pcie_root_config_read()
180         val = root->atu_viewport;  in designware_pcie_root_config_read()
221     DesignwarePCIERoot *root = viewport->root;  in designware_pcie_root_data_access()  local
225     PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));  in designware_pcie_root_data_access()
267 static void designware_pcie_update_viewport(DesignwarePCIERoot *root,  in designware_pcie_update_viewport()  argument
302     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);  in designware_pcie_root_config_write()  local
303     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_config_write()
305         designware_pcie_root_get_current_viewport(root);  in designware_pcie_root_config_write()
315         root->msi.base &= 0xFFFFFFFF00000000ULL;  in designware_pcie_root_config_write()
316         root->msi.base |= val;  in designware_pcie_root_config_write()
317         designware_pcie_root_update_msi_mapping(root);  in designware_pcie_root_config_write()
321         root->msi.base &= 0x00000000FFFFFFFFULL;  in designware_pcie_root_config_write()
322         root->msi.base |= (uint64_t)val << 32;  in designware_pcie_root_config_write()
323         designware_pcie_root_update_msi_mapping(root);  in designware_pcie_root_config_write()
327         root->msi.intr[0].enable = val;  in designware_pcie_root_config_write()
328         designware_pcie_root_update_msi_mapping(root);  in designware_pcie_root_config_write()
332         root->msi.intr[0].mask = val;  in designware_pcie_root_config_write()
336         root->msi.intr[0].status ^= val;  in designware_pcie_root_config_write()
337         if (!root->msi.intr[0].status) {  in designware_pcie_root_config_write()
345         root->atu_viewport = val;  in designware_pcie_root_config_write()
377         designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_config_write()
396     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);  in designware_pcie_root_realize()  local
397     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_realize()
430         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];  in designware_pcie_root_realize()
447         memory_region_init_alias(mem, OBJECT(root), name, destination,  in designware_pcie_root_realize()
453         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];  in designware_pcie_root_realize()
454         viewport->root    = root;  in designware_pcie_root_realize()
471         memory_region_init_alias(mem, OBJECT(root), name, destination,  in designware_pcie_root_realize()
483         memory_region_init_io(&viewport->cfg, OBJECT(root),  in designware_pcie_root_realize()
500     viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];  in designware_pcie_root_realize()
502     designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_realize()
504     memory_region_init_io(&root->msi.iomem, OBJECT(root),  in designware_pcie_root_realize()
506                           root, "pcie-msi", 0x4);  in designware_pcie_root_realize()
513     memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);  in designware_pcie_root_realize()
514     memory_region_set_enabled(&root->msi.iomem, false);  in designware_pcie_root_realize()
716     qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);  in designware_pcie_host_realize()
724         VMSTATE_STRUCT(root,
748     DesignwarePCIERoot *root = &s->root;  in designware_pcie_host_init()  local
750     object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT);  in designware_pcie_host_init()
751     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));  in designware_pcie_host_init()
752     qdev_prop_set_bit(DEVICE(root), "multifunction", false);  in designware_pcie_host_init()