hw/pci-host/designware.c

64      * Designware has only a single root complex. Enforce the limit on the  in designware_pcie_root_bus_class_init()
71 designware_pcie_root_to_host(DesignwarePCIERoot *root)  in designware_pcie_root_to_host()  argument
73     BusState *bus = qdev_get_parent_bus(DEVICE(root));  in designware_pcie_root_to_host()
97     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);  in designware_pcie_root_msi_write()  local
98     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_msi_write()
100     root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;  in designware_pcie_root_msi_write()
102     if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {  in designware_pcie_root_msi_write()
117 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)  in designware_pcie_root_update_msi_mapping()  argument
120     MemoryRegion *mem   = &root->msi.iomem;  in designware_pcie_root_update_msi_mapping()
121     const uint64_t base = root->msi.base;  in designware_pcie_root_update_msi_mapping()
122     const bool enable   = root->msi.intr[0].enable;  in designware_pcie_root_update_msi_mapping()
129 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)  in designware_pcie_root_get_current_viewport()  argument
131     const unsigned int idx = root->atu_viewport & 0xF;  in designware_pcie_root_get_current_viewport()
133         !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);  in designware_pcie_root_get_current_viewport()
134     return &root->viewports[dir][idx];  in designware_pcie_root_get_current_viewport()
140     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);  in designware_pcie_root_config_read()  local
142         designware_pcie_root_get_current_viewport(root);  in designware_pcie_root_config_read()
167         val = extract64(root->msi.base,  in designware_pcie_root_config_read()
172         val = root->msi.intr[0].enable;  in designware_pcie_root_config_read()
176         val = root->msi.intr[0].mask;  in designware_pcie_root_config_read()
180         val = root->msi.intr[0].status;  in designware_pcie_root_config_read()
188         val = root->atu_viewport;  in designware_pcie_root_config_read()
226     DesignwarePCIERoot *root = viewport->root;  in designware_pcie_root_data_access()  local
230     PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));  in designware_pcie_root_data_access()
272 static void designware_pcie_update_viewport(DesignwarePCIERoot *root,  in designware_pcie_update_viewport()  argument
307     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);  in designware_pcie_root_config_write()  local
308     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_config_write()
310         designware_pcie_root_get_current_viewport(root);  in designware_pcie_root_config_write()
321         root->msi.base = deposit64(root->msi.base,  in designware_pcie_root_config_write()
324         designware_pcie_root_update_msi_mapping(root);  in designware_pcie_root_config_write()
328         root->msi.intr[0].enable = val;  in designware_pcie_root_config_write()
329         designware_pcie_root_update_msi_mapping(root);  in designware_pcie_root_config_write()
333         root->msi.intr[0].mask = val;  in designware_pcie_root_config_write()
337         root->msi.intr[0].status ^= val;  in designware_pcie_root_config_write()
338         if (!root->msi.intr[0].status) {  in designware_pcie_root_config_write()
346         root->atu_viewport = val;  in designware_pcie_root_config_write()
372         designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_config_write()
391     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);  in designware_pcie_root_realize()  local
392     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);  in designware_pcie_root_realize()
426         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];  in designware_pcie_root_realize()
443         memory_region_init_alias(mem, OBJECT(root), name, destination,  in designware_pcie_root_realize()
449         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];  in designware_pcie_root_realize()
450         viewport->root    = root;  in designware_pcie_root_realize()
467         memory_region_init_alias(mem, OBJECT(root), name, destination,  in designware_pcie_root_realize()
479         memory_region_init_io(&viewport->cfg, OBJECT(root),  in designware_pcie_root_realize()
496     viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];  in designware_pcie_root_realize()
498     designware_pcie_update_viewport(root, viewport);  in designware_pcie_root_realize()
500     memory_region_init_io(&root->msi.iomem, OBJECT(root),  in designware_pcie_root_realize()
502                           root, "pcie-msi", 0x4);  in designware_pcie_root_realize()
509     memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);  in designware_pcie_root_realize()
510     memory_region_set_enabled(&root->msi.iomem, false);  in designware_pcie_root_realize()
568     .name = "designware-pcie-root",
705                        "pcie-bus-address-space-root",  in designware_pcie_host_realize()
714     qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);  in designware_pcie_host_realize()
722         VMSTATE_STRUCT(root,
747     DesignwarePCIERoot *root = &s->root;  in designware_pcie_host_init()  local
749     object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT);  in designware_pcie_host_init()
750     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));  in designware_pcie_host_init()
751     qdev_prop_set_bit(DEVICE(root), "multifunction", false);  in designware_pcie_host_init()