Lines Matching refs:rpc
149 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); in cxl_rp_realize() local
156 rpc->parent_realize(dev, &local_err); in cxl_rp_realize()
165 rpc->parent_class.exit(pci_dev); in cxl_rp_realize()
191 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); in cxl_rp_reset_hold() local
194 if (rpc->parent_phases.hold) { in cxl_rp_reset_hold()
195 rpc->parent_phases.hold(obj); in cxl_rp_reset_hold()
236 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); in cxl_rp_aer_vector_update() local
238 if (rpc->aer_vector) { in cxl_rp_aer_vector_update()
239 pcie_aer_root_set_vector(d, rpc->aer_vector(d)); in cxl_rp_aer_vector_update()
266 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc); in cxl_root_port_class_init() local
275 device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize); in cxl_root_port_class_init()
277 &rpc->parent_phases); in cxl_root_port_class_init()
279 rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; in cxl_root_port_class_init()
280 rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; in cxl_root_port_class_init()
281 rpc->aer_vector = cxl_rp_aer_vector; in cxl_root_port_class_init()
282 rpc->interrupts_init = cxl_rp_interrupts_init; in cxl_root_port_class_init()
283 rpc->interrupts_uninit = cxl_rp_interrupts_uninit; in cxl_root_port_class_init()