133     char *nodename;  in openrisc_create_fdt()  local
152     nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,  in openrisc_create_fdt()
154     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
155     qemu_fdt_setprop_cells(fdt, nodename, "reg",  in openrisc_create_fdt()
157     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");  in openrisc_create_fdt()
158     g_free(nodename);  in openrisc_create_fdt()
165         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);  in openrisc_create_fdt()
166         qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
167         qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_create_fdt()
169         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);  in openrisc_create_fdt()
170         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",  in openrisc_create_fdt()
172         g_free(nodename);  in openrisc_create_fdt()
175     nodename = (char *)"/pic";  in openrisc_create_fdt()
176     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
178     qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_create_fdt()
180     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);  in openrisc_create_fdt()
181     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_create_fdt()
182     qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);  in openrisc_create_fdt()
206     char *nodename;  in openrisc_virt_ompic_init()  local
220     nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);  in openrisc_virt_ompic_init()
221     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_ompic_init()
222     qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");  in openrisc_virt_ompic_init()
223     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_virt_ompic_init()
224     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_virt_ompic_init()
225     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);  in openrisc_virt_ompic_init()
226     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_virt_ompic_init()
227     g_free(nodename);  in openrisc_virt_ompic_init()
235     char *nodename;  in openrisc_virt_serial_init()  local
242     nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);  in openrisc_virt_serial_init()
243     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_serial_init()
244     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");  in openrisc_virt_serial_init()
245     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_virt_serial_init()
246     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_virt_serial_init()
247     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);  in openrisc_virt_serial_init()
248     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_virt_serial_init()
251     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);  in openrisc_virt_serial_init()
252     qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);  in openrisc_virt_serial_init()
253     g_free(nodename);  in openrisc_virt_serial_init()
261     char *nodename;  in openrisc_virt_test_init()  local
267     nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);  in openrisc_virt_test_init()
268     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_test_init()
269     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");  in openrisc_virt_test_init()
271     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_virt_test_init()
272     qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);  in openrisc_virt_test_init()
273     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_virt_test_init()
274     g_free(nodename);  in openrisc_virt_test_init()
276     nodename = g_strdup_printf("/soc/reboot");  in openrisc_virt_test_init()
277     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_test_init()
278     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");  in openrisc_virt_test_init()
279     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);  in openrisc_virt_test_init()
280     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);  in openrisc_virt_test_init()
281     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);  in openrisc_virt_test_init()
282     g_free(nodename);  in openrisc_virt_test_init()
284     nodename = g_strdup_printf("/soc/poweroff");  in openrisc_virt_test_init()
285     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_test_init()
286     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");  in openrisc_virt_test_init()
287     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);  in openrisc_virt_test_init()
288     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);  in openrisc_virt_test_init()
289     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);  in openrisc_virt_test_init()
290     g_free(nodename);  in openrisc_virt_test_init()
299     char *nodename;  in openrisc_virt_rtc_init()  local
306     nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);  in openrisc_virt_rtc_init()
307     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_rtc_init()
308     qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_virt_rtc_init()
310     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_virt_rtc_init()
311     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_virt_rtc_init()
312     g_free(nodename);  in openrisc_virt_rtc_init()
316 static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,  in create_pcie_irq_map()  argument
359     qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,  in create_pcie_irq_map()
363     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",  in create_pcie_irq_map()
375     char *nodename;  in openrisc_virt_pcie_init()  local
419     nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);  in openrisc_virt_pcie_init()
420     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_pcie_init()
421     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);  in openrisc_virt_pcie_init()
422     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);  in openrisc_virt_pcie_init()
423     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);  in openrisc_virt_pcie_init()
424     qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_virt_pcie_init()
426     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");  in openrisc_virt_pcie_init()
427     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);  in openrisc_virt_pcie_init()
428     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,  in openrisc_virt_pcie_init()
430     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);  in openrisc_virt_pcie_init()
431     qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);  in openrisc_virt_pcie_init()
433     qemu_fdt_setprop_cells(fdt, nodename, "ranges",  in openrisc_virt_pcie_init()
439     create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);  in openrisc_virt_pcie_init()
440     g_free(nodename);  in openrisc_virt_pcie_init()
448     char *nodename;  in openrisc_virt_virtio_init()  local
462     nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);  in openrisc_virt_virtio_init()
463     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_virt_virtio_init()
464     qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");  in openrisc_virt_virtio_init()
465     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_virt_virtio_init()
466     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_virt_virtio_init()
467     g_free(nodename);  in openrisc_virt_virtio_init()