4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
22 #include "qemu/error-report.h"
27 #include "hw/char/serial-mm.h"
30 #include "hw/qdev-properties.h"
31 #include "system/address-spaces.h"
37 #include "hw/core/split-irq.h"
46 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
100     cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);  in main_cpu_reset()
108 static void openrisc_create_fdt(Or1ksimState *state,  in openrisc_create_fdt()  argument
118     fdt = state->fdt = create_device_tree(&state->fdt_size);  in openrisc_create_fdt()
125     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);  in openrisc_create_fdt()
126     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);  in openrisc_create_fdt()
137     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);  in openrisc_create_fdt()
138     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);  in openrisc_create_fdt()
144                                 "opencores,or1200-rtlsvn481");  in openrisc_create_fdt()
146         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",  in openrisc_create_fdt()
155                             "opencores,or1k-pic-level");  in openrisc_create_fdt()
156     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);  in openrisc_create_fdt()
157     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_create_fdt()
160     qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);  in openrisc_create_fdt()
171 static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size,  in openrisc_sim_net_init()  argument
175     void *fdt = state->fdt;  in openrisc_sim_net_init()
190         qdev_prop_set_uint32(splitter, "num-lines", num_cpus);  in openrisc_sim_net_init()
208     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_sim_net_init()
214 static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,  in openrisc_sim_ompic_init()  argument
218     void *fdt = state->fdt;  in openrisc_sim_ompic_init()
224     dev = qdev_new("or1k-ompic");  in openrisc_sim_ompic_init()
225     qdev_prop_set_uint32(dev, "num-cpus", num_cpus);  in openrisc_sim_ompic_init()
239     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_sim_ompic_init()
240     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);  in openrisc_sim_ompic_init()
245 static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,  in openrisc_sim_serial_init()  argument
250     void *fdt = state->fdt;  in openrisc_sim_serial_init()
258         qdev_prop_set_uint32(splitter, "num-lines", num_cpus);  in openrisc_sim_serial_init()
271     /* Add device tree node for serial. */  in openrisc_sim_serial_init()
272     nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);  in openrisc_sim_serial_init()
277     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);  in openrisc_sim_serial_init()
278     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_sim_serial_init()
282         qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);  in openrisc_sim_serial_init()
284     snprintf(alias, sizeof(alias), "serial%d", uart_idx);  in openrisc_sim_serial_init()
292     ram_addr_t ram_size = machine->ram_size;  in openrisc_sim_init()
293     const char *kernel_filename = machine->kernel_filename;  in openrisc_sim_init()
295     Or1ksimState *state = OR1KSIM_MACHINE(machine);  in openrisc_sim_init()  local
299     unsigned int smp_cpus = machine->smp.cpus;  in openrisc_sim_init()
303         cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));  in openrisc_sim_init()
316     openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size,  in openrisc_sim_init()
317                         machine->kernel_cmdline);  in openrisc_sim_init()
319     openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base,  in openrisc_sim_init()
325         openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,  in openrisc_sim_init()
333      * DTB in reverse order of creation. Correctly-written guest software  in openrisc_sim_init()
334      * will not care about the node order (it will look at stdout-path  in openrisc_sim_init()
337      * lowest-address UART (which is QEMU's first serial port) appears  in openrisc_sim_init()
340     for (n = OR1KSIM_UART_COUNT - 1; n >= 0; n--) {  in openrisc_sim_init()
341         openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +  in openrisc_sim_init()
350         if (machine->initrd_filename) {  in openrisc_sim_init()
351             load_addr = openrisc_load_initrd(state->fdt,  in openrisc_sim_init()
352                                              machine->initrd_filename,  in openrisc_sim_init()
353                                              load_addr, machine->ram_size);  in openrisc_sim_init()
355         boot_info.fdt_addr = openrisc_load_fdt(machine, state->fdt, load_addr,  in openrisc_sim_init()
356                                                machine->ram_size);  in openrisc_sim_init()
364     mc->desc = "or1k simulation";  in openrisc_sim_machine_init()
365     mc->init = openrisc_sim_init;  in openrisc_sim_machine_init()
366     mc->max_cpus = OR1KSIM_CPUS_MAX;  in openrisc_sim_machine_init()
367     mc->is_default = true;  in openrisc_sim_machine_init()
368     mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");  in openrisc_sim_machine_init()