115     char *nodename;  in openrisc_create_fdt()  local
128     nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,  in openrisc_create_fdt()
130     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
131     qemu_fdt_setprop_cells(fdt, nodename, "reg",  in openrisc_create_fdt()
133     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");  in openrisc_create_fdt()
134     g_free(nodename);  in openrisc_create_fdt()
141         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);  in openrisc_create_fdt()
142         qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
143         qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_create_fdt()
145         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);  in openrisc_create_fdt()
146         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",  in openrisc_create_fdt()
148         g_free(nodename);  in openrisc_create_fdt()
151     nodename = (char *)"/pic";  in openrisc_create_fdt()
152     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_create_fdt()
154     qemu_fdt_setprop_string(fdt, nodename, "compatible",  in openrisc_create_fdt()
156     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);  in openrisc_create_fdt()
157     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_create_fdt()
158     qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);  in openrisc_create_fdt()
178     char *nodename;  in openrisc_sim_net_init()  local
203     nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base);  in openrisc_sim_net_init()
204     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_sim_net_init()
205     qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc");  in openrisc_sim_net_init()
206     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_sim_net_init()
207     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_sim_net_init()
208     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_sim_net_init()
210     qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename);  in openrisc_sim_net_init()
211     g_free(nodename);  in openrisc_sim_net_init()
221     char *nodename;  in openrisc_sim_ompic_init()  local
235     nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);  in openrisc_sim_ompic_init()
236     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_sim_ompic_init()
237     qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");  in openrisc_sim_ompic_init()
238     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_sim_ompic_init()
239     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);  in openrisc_sim_ompic_init()
240     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);  in openrisc_sim_ompic_init()
241     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_sim_ompic_init()
242     g_free(nodename);  in openrisc_sim_ompic_init()
251     char *nodename;  in openrisc_sim_serial_init()  local
272     nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);  in openrisc_sim_serial_init()
273     qemu_fdt_add_subnode(fdt, nodename);  in openrisc_sim_serial_init()
274     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");  in openrisc_sim_serial_init()
275     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);  in openrisc_sim_serial_init()
276     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);  in openrisc_sim_serial_init()
277     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);  in openrisc_sim_serial_init()
278     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);  in openrisc_sim_serial_init()
282         qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);  in openrisc_sim_serial_init()
285     qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);  in openrisc_sim_serial_init()
287     g_free(nodename);  in openrisc_sim_serial_init()