4  * Copyright (c) 2014-2021 Xilinx Inc.
27 #include "hw/nvram/xlnx-bbram.h"
29 #include "qemu/error-report.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
36 #include "hw/nvram/xlnx-efuse.h"
75 #define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
79 QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
83     return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;  in bbram_msw_locked()
88     return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;  in bbram_pgm_enabled()
95     error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",  in bbram_bdrv_error()
96                      blk_name(s->blk), detail);  in bbram_bdrv_error()
105     uint32_t *ram = &s->regs[R_BBRAM_0];  in bbram_bdrv_read()
108     if (!s->blk) {  in bbram_bdrv_read()
112     s->blk_ro = !blk_supports_write_perm(s->blk);  in bbram_bdrv_read()
113     if (!s->blk_ro) {  in bbram_bdrv_read()
116         rc = blk_set_perm(s->blk,  in bbram_bdrv_read()
120             s->blk_ro = true;  in bbram_bdrv_read()
123     if (s->blk_ro) {  in bbram_bdrv_read()
124         warn_report("%s: Skip saving updates to read-only BBRAM backstore.",  in bbram_bdrv_read()
125                     blk_name(s->blk));  in bbram_bdrv_read()
128     if (blk_pread(s->blk, 0, nr, ram, 0) < 0) {  in bbram_bdrv_read()
131                    blk_name(s->blk), nr);  in bbram_bdrv_read()
135     /* Convert from little-endian backstore for each 32-bit word */  in bbram_bdrv_read()
137     while (nr--) {  in bbram_bdrv_read()
150     /* Backstore is always in little-endian */  in bbram_bdrv_sync()
151     le32 = cpu_to_le32(s->regs[hwaddr / 4]);  in bbram_bdrv_sync()
154     if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {  in bbram_bdrv_sync()
155         ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);  in bbram_bdrv_sync()
158     if (!s->blk || s->blk_ro) {  in bbram_bdrv_sync()
162     offset = hwaddr - A_BBRAM_0;  in bbram_bdrv_sync()
163     rc = blk_pwrite(s->blk, offset, 4, &le32, 0);  in bbram_bdrv_sync()
173     ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);  in bbram_bdrv_zero()
175     if (!s->blk || s->blk_ro) {  in bbram_bdrv_zero()
179     rc = blk_make_zero(s->blk, 0);  in bbram_bdrv_zero()
184     /* Restore bbram8 if it is non-zero */  in bbram_bdrv_zero()
185     if (s->regs[R_BBRAM_8]) {  in bbram_bdrv_zero()
192     int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */  in bbram_zeroize()
194     memset(&s->regs[R_BBRAM_0], 0, nr);  in bbram_zeroize()
200     bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];  in bbram_update_irq()
202     qemu_set_irq(s->irq_bbram, pending);  in bbram_update_irq()
207     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_ctrl_postw()
213         s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;  in bbram_ctrl_postw()
219     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_pgm_mode_postw()
226         ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);  in bbram_pgm_mode_postw()
232     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_aes_crc_postw()
240     /* Perform the AES integrity check */  in bbram_aes_crc_postw()
241     s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;  in bbram_aes_crc_postw()
246      * ZynqMP BBRAM check has a zero-u32 prepended; see:  in bbram_aes_crc_postw()
247 …*  https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bb…  in bbram_aes_crc_postw()
249     calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],  in bbram_aes_crc_postw()
250                                    (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);  in bbram_aes_crc_postw()
252     ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,  in bbram_aes_crc_postw()
253                      (s->regs[R_BBRAM_AES_CRC] == calc_crc));  in bbram_aes_crc_postw()
258     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_key_prew()
259     uint32_t original_data = *(uint32_t *) reg->data;  in bbram_key_prew()
273     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_key_postw()
275     bbram_bdrv_sync(s, reg->access->addr);  in bbram_key_postw()
285     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_r8_postr()
287     return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;  in bbram_r8_postr()
297     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_r8_prew()
300         val64 = *(uint32_t *)reg->data;  in bbram_r8_prew()
308     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_r8_postw()
317     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_msw_lock_prew()
320     if (s->bbram8_wo) {  in bbram_msw_lock_prew()
323         val64 |= s->regs[R_BBRAM_MSW_LOCK];  in bbram_msw_lock_prew()
331     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_isr_postw()
338     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_ier_prew()
341     s->regs[R_BBRAM_IMR] &= ~val;  in bbram_ier_prew()
348     XlnxBBRam *s = XLNX_BBRAM(reg->opaque);  in bbram_idr_prew()
351     s->regs[R_BBRAM_IMR] |= val;  in bbram_idr_prew()
425     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {  in bbram_ctrl_reset_hold()
427             register_reset(&s->regs_info[i]);  in bbram_ctrl_reset_hold()
448     if (s->crc_zpads) {  in bbram_ctrl_realize()
449         s->bbram8_wo = true;  in bbram_ctrl_realize()
460     s->reg_array =  in bbram_ctrl_init()
463                               s->regs_info, s->regs,  in bbram_ctrl_init()
468     sysbus_init_mmio(sbd, &s->reg_array->mem);  in bbram_ctrl_init()
469     sysbus_init_irq(sbd, &s->irq_bbram);  in bbram_ctrl_init()
476     register_finalize_block(s->reg_array);  in bbram_ctrl_finalize()
487     if (dev->realized) {  in bbram_prop_set_drive()
525     DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
534     rc->phases.hold = bbram_ctrl_reset_hold;  in bbram_ctrl_class_init()
535     dc->realize = bbram_ctrl_realize;  in bbram_ctrl_class_init()
536     dc->vmsd = &vmstate_bbram_ctrl;  in bbram_ctrl_class_init()