58  * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
60  * device will use the "v1.4 CMB scheme" - use the `legacy-cmb` parameter to
519     if (!n->cmb.cmse) {  in nvme_addr_is_cmb()
523     lo = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba;  in nvme_addr_is_cmb()
524     hi = lo + int128_get64(n->cmb.mem.size);  in nvme_addr_is_cmb()
531     hwaddr base = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba;  in nvme_addr_to_cmb()
532     return &n->cmb.buf[addr - base];  in nvme_addr_to_cmb()
562      * that if the device model is ever changed to allow the CMB to be located  in nvme_addr_is_iomem()
829     bool cmb = false, pmr = false;  in nvme_map_addr()  local
842         cmb = true;  in nvme_map_addr()
847     if (cmb || pmr) {  in nvme_map_addr()
856         if (cmb) {  in nvme_map_addr()
7837         n->cmb.cmse = false;  in nvme_write_bar()
7845                 if (cba + int128_get64(n->cmb.mem.size) < cba) {  in nvme_write_bar()
7852                 n->cmb.cba = cba;  in nvme_write_bar()
7853                 n->cmb.cmse = true;  in nvme_write_bar()
8162     stn_le_p(&n->cmb.buf[addr], size, data);  in nvme_cmb_write()
8168     return ldn_le_p(&n->cmb.buf[addr], size);  in nvme_cmb_read()
8260             error_setg(errp, "CMB is not supported with SR-IOV");  in nvme_check_params()
8415     n->cmb.buf = g_malloc0(cmb_size);  in nvme_init_cmb()
8416     memory_region_init_io(&n->cmb.mem, OBJECT(n), &nvme_cmb_ops, n,  in nvme_init_cmb()
8417                           "nvme-cmb", cmb_size);  in nvme_init_cmb()
8421                      PCI_BASE_ADDRESS_MEM_PREFETCH, &n->cmb.mem);  in nvme_init_cmb()
8428         n->cmb.cmse = true;  in nvme_init_cmb()
8905         g_free(n->cmb.buf);  in nvme_exit()
8946     DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),