Lines Matching +full:conf +full:- +full:ds
2 * QEMU model of Xilinx AXI-Ethernet.
35 #include "hw/qdev-properties.h"
41 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
42 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
43 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
55 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
56 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
57 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
81 if (!phy->link) { in tdk_read()
99 r |= phy->regs[4] & (15 << 5); in tdk_read()
113 if (!phy->link) { in tdk_read()
118 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); in tdk_read()
119 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); in tdk_read()
122 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); in tdk_read()
123 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); in tdk_read()
129 r = phy->regs[regnum]; in tdk_read()
145 phy->regs[regnum] = data; in tdk_write()
149 /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ in tdk_write()
150 phy->regs[0] &= ~0x8200; in tdk_write()
156 phy->regs[0] = 0x3100; in tdk_init()
158 phy->regs[2] = 0x0300; in tdk_init()
159 phy->regs[3] = 0xe400; in tdk_init()
161 phy->regs[4] = 0x01E1; in tdk_init()
162 phy->link = 1; in tdk_init()
164 phy->read = tdk_read; in tdk_init()
165 phy->write = tdk_write; in tdk_init()
175 bus->devs[addr & 0x1f] = phy; in mdio_attach()
182 bus->devs[addr & 0x1f] = NULL; in mdio_detach()
192 phy = bus->devs[addr]; in mdio_read_req()
193 if (phy && phy->read) { in mdio_read_req()
194 data = phy->read(phy, reg); in mdio_read_req()
208 phy = bus->devs[addr]; in mdio_write_req()
209 if (phy && phy->write) { in mdio_write_req()
210 phy->write(phy, reg, data); in mdio_write_req()
327 NICConf conf; member
394 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; in axienet_rx_reset()
399 s->tc = TC_JUM | TC_TX | TC_VLAN; in axienet_tx_reset()
400 s->txpos = 0; in axienet_tx_reset()
405 return s->rcw[1] & RCW1_RST; in axienet_rx_resetting()
410 return s->rcw[1] & RCW1_RX; in axienet_rx_enabled()
415 return !!(s->regs[R_RAF] & RAF_EMCF_EN); in axienet_extmcf_enabled()
420 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); in axienet_newfunc_enabled()
430 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; in xilinx_axienet_reset()
431 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; in xilinx_axienet_reset()
433 s->emmc = EMMC_LINKSPEED_100MB; in xilinx_axienet_reset()
438 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; in enet_update_irq()
439 qemu_set_irq(s->irq, !!s->regs[R_IP]); in enet_update_irq()
451 r = s->rcw[addr & 1]; in enet_read()
455 r = s->tc; in enet_read()
459 r = s->emmc; in enet_read()
463 r = s->phyc; in enet_read()
467 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ in enet_read()
472 r = s->stats.rx_bytes >> (32 * (addr & 1)); in enet_read()
477 r = s->stats.tx_bytes >> (32 * (addr & 1)); in enet_read()
482 r = s->stats.rx >> (32 * (addr & 1)); in enet_read()
486 r = s->stats.rx_bcast >> (32 * (addr & 1)); in enet_read()
490 r = s->stats.rx_mcast >> (32 * (addr & 1)); in enet_read()
496 r = s->mii.regs[addr & 3]; in enet_read()
501 r = s->uaw[addr & 1]; in enet_read()
506 r = s->ext_uaw[addr & 1]; in enet_read()
510 r = s->fmi; in enet_read()
515 r = s->maddr[s->fmi & 3][addr & 1]; in enet_read()
519 r = s->ext_mtable[addr - 0x8000]; in enet_read()
523 if (addr < ARRAY_SIZE(s->regs)) { in enet_read()
524 r = s->regs[addr]; in enet_read()
537 struct TEMAC *t = &s->TEMAC; in enet_write()
543 s->rcw[addr & 1] = value; in enet_write()
547 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in enet_write()
552 s->tc = value; in enet_write()
559 s->emmc = value; in enet_write()
563 s->phyc = value; in enet_write()
567 value &= ((1 << 7) - 1); in enet_write()
571 unsigned int miiclkdiv = value & ((1 << 6) - 1); in enet_write()
576 s->mii.mc = value; in enet_write()
587 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); in enet_write()
589 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); in enet_write()
594 s->mii.mcr = value; in enet_write()
600 s->mii.regs[addr & 3] = value; in enet_write()
606 s->uaw[addr & 1] = value; in enet_write()
611 s->ext_uaw[addr & 1] = value; in enet_write()
615 s->fmi = value; in enet_write()
620 s->maddr[s->fmi & 3][addr & 1] = value; in enet_write()
624 s->regs[addr] &= ~value; in enet_write()
628 s->ext_mtable[addr - 0x8000] = value; in enet_write()
634 if (addr < ARRAY_SIZE(s->regs)) { in enet_write()
635 s->regs[addr] = value; in enet_write()
651 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); in eth_can_rx()
673 while (s->rxappsize && stream_can_push(s->tx_control_dev, in axienet_eth_rx_notify()
675 size_t ret = stream_push(s->tx_control_dev, in axienet_eth_rx_notify()
676 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE in axienet_eth_rx_notify()
677 - s->rxappsize, s->rxappsize, true); in axienet_eth_rx_notify()
678 s->rxappsize -= ret; in axienet_eth_rx_notify()
681 while (s->rxsize && stream_can_push(s->tx_data_dev, in axienet_eth_rx_notify()
683 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, in axienet_eth_rx_notify()
684 s->rxsize, true); in axienet_eth_rx_notify()
685 s->rxsize -= ret; in axienet_eth_rx_notify()
686 s->rxpos += ret; in axienet_eth_rx_notify()
687 if (!s->rxsize) { in axienet_eth_rx_notify()
688 s->regs[R_IS] |= IS_RX_COMPLETE; in axienet_eth_rx_notify()
689 if (s->need_flush) { in axienet_eth_rx_notify()
690 s->need_flush = false; in axienet_eth_rx_notify()
691 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in axienet_eth_rx_notify()
705 int promisc = s->fmi & (1 << 31); in eth_rx()
714 s->need_flush = true; in eth_rx()
726 if (!(s->rcw[1] & RCW1_JUM)) { in eth_rx()
727 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { in eth_rx()
737 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { in eth_rx()
743 if (s->regs[R_RAF] & RAF_BCAST_REJ) { in eth_rx()
750 if (s->regs[R_RAF] & RAF_MCAST_REJ) { in eth_rx()
755 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { in eth_rx()
771 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { in eth_rx()
777 if (s->regs[R_RAF] & RAF_BCAST_REJ) { in eth_rx()
794 if (!(s->ext_mtable[idx] & bit)) { in eth_rx()
802 s->regs[R_IS] |= IS_RX_REJECT; in eth_rx()
804 return -1; in eth_rx()
807 if (size > (s->c_rxmem - 4)) { in eth_rx()
808 size = s->c_rxmem - 4; in eth_rx()
811 memcpy(s->rxmem, buf, size); in eth_rx()
812 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ in eth_rx()
814 if (s->rcw[1] & RCW1_FCS) { in eth_rx()
819 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); in eth_rx()
827 s->stats.rx_bytes += size; in eth_rx()
828 s->stats.rx++; in eth_rx()
830 s->stats.rx_mcast++; in eth_rx()
833 s->stats.rx_bcast++; in eth_rx()
840 s->rxsize = size; in eth_rx()
841 s->rxpos = 0; in eth_rx()
845 s->rxappsize = CONTROL_PAYLOAD_SIZE; in eth_rx()
846 memcpy(s->rxapp, app, s->rxappsize); in eth_rx()
850 return s->rxpos; in eth_rx()
859 XilinxAXIEnet *s = cs->enet; in xilinx_axienet_control_stream_push()
867 memcpy(s->hdr, buf, len); in xilinx_axienet_control_stream_push()
869 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { in xilinx_axienet_control_stream_push()
870 s->hdr[i] = le32_to_cpu(s->hdr[i]); in xilinx_axienet_control_stream_push()
879 XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj); in xilinx_axienet_data_stream_push() local
880 XilinxAXIEnet *s = ds->enet; in xilinx_axienet_data_stream_push()
883 if (!(s->tc & TC_TX)) { in xilinx_axienet_data_stream_push()
887 if (s->txpos + size > s->c_txmem) { in xilinx_axienet_data_stream_push()
890 s->txpos = 0; in xilinx_axienet_data_stream_push()
894 if (s->txpos == 0 && eop) { in xilinx_axienet_data_stream_push()
896 s->txpos = size; in xilinx_axienet_data_stream_push()
898 memcpy(s->txmem + s->txpos, buf, size); in xilinx_axienet_data_stream_push()
899 buf = s->txmem; in xilinx_axienet_data_stream_push()
900 s->txpos += size; in xilinx_axienet_data_stream_push()
908 if (!(s->tc & TC_JUM)) { in xilinx_axienet_data_stream_push()
909 if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { in xilinx_axienet_data_stream_push()
910 s->txpos = 0; in xilinx_axienet_data_stream_push()
915 if (s->hdr[0] & 1) { in xilinx_axienet_data_stream_push()
916 unsigned int start_off = s->hdr[1] >> 16; in xilinx_axienet_data_stream_push()
917 unsigned int write_off = s->hdr[1] & 0xffff; in xilinx_axienet_data_stream_push()
921 tmp_csum = net_checksum_add(s->txpos - start_off, in xilinx_axienet_data_stream_push()
924 tmp_csum += s->hdr[2] & 0xffff; in xilinx_axienet_data_stream_push()
934 qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); in xilinx_axienet_data_stream_push()
936 s->stats.tx_bytes += s->txpos; in xilinx_axienet_data_stream_push()
937 s->regs[R_IS] |= IS_TX_COMPLETE; in xilinx_axienet_data_stream_push()
940 s->txpos = 0; in xilinx_axienet_data_stream_push()
953 XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); in xilinx_enet_realize() local
955 &s->rx_control_dev); in xilinx_enet_realize()
957 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", in xilinx_enet_realize()
958 (Object **) &ds->enet, in xilinx_enet_realize()
961 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", in xilinx_enet_realize()
962 (Object **) &cs->enet, in xilinx_enet_realize()
965 object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); in xilinx_enet_realize()
968 qemu_macaddr_default_if_unset(&s->conf.macaddr); in xilinx_enet_realize()
969 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, in xilinx_enet_realize()
970 object_get_typename(OBJECT(dev)), dev->id, in xilinx_enet_realize()
971 &dev->mem_reentrancy_guard, s); in xilinx_enet_realize()
972 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in xilinx_enet_realize()
974 tdk_init(&s->TEMAC.phy); in xilinx_enet_realize()
975 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); in xilinx_enet_realize()
977 s->TEMAC.parent = s; in xilinx_enet_realize()
979 s->rxmem = g_malloc(s->c_rxmem); in xilinx_enet_realize()
980 s->txmem = g_malloc(s->c_txmem); in xilinx_enet_realize()
988 object_initialize_child(OBJECT(s), "axistream-connected-target", in xilinx_enet_init()
989 &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); in xilinx_enet_init()
990 object_initialize_child(OBJECT(s), "axistream-control-connected-target", in xilinx_enet_init()
991 &s->rx_control_dev, in xilinx_enet_init()
993 sysbus_init_irq(sbd, &s->irq); in xilinx_enet_init()
995 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); in xilinx_enet_init()
996 sysbus_init_mmio(sbd, &s->iomem); in xilinx_enet_init()
1003 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
1004 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
1006 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
1015 dc->realize = xilinx_enet_realize; in xilinx_enet_class_init()
1025 ssc->push = xilinx_axienet_control_stream_push; in xilinx_enet_control_stream_class_init()
1032 ssc->push = xilinx_axienet_data_stream_push; in xilinx_enet_data_stream_class_init()