Lines Matching +full:conf +full:- +full:ds
4 * Copyright (c) 2017 Mark Cave-Ayland
27 #include "hw/qdev-properties.h"
162 NICConf conf; member
181 DEFINE_NIC_PROPERTIES(SunHMEState, conf),
188 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ETX; in sunhme_reset_tx()
194 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ERX; in sunhme_reset_rx()
202 /* MIF interrupt mask (16-bit) */ in sunhme_update_irq()
203 uint32_t mifmask = ~(s->mifregs[HME_MIFI_IMASK >> 2]) & 0xffff; in sunhme_update_irq()
204 uint32_t mif = s->mifregs[HME_MIFI_STAT >> 2] & mifmask; in sunhme_update_irq()
207 uint32_t sebmask = ~(s->sebregs[HME_SEBI_IMASK >> 2]) & in sunhme_update_irq()
209 uint32_t seb = s->sebregs[HME_SEBI_STAT >> 2] & sebmask; in sunhme_update_irq()
248 val = s->sebregs[HME_SEBI_RESET >> 2]; in sunhme_seb_write()
252 s->sebregs[addr >> 2] = val; in sunhme_seb_write()
274 val = s->sebregs[addr >> 2]; in sunhme_seb_read()
279 s->sebregs[HME_SEBI_STAT >> 2] &= HME_SEB_STAT_MIFIRQ; in sunhme_seb_read()
316 s->etxregs[addr >> 2] = val; in sunhme_etx_write()
325 val = s->etxregs[addr >> 2]; in sunhme_etx_read()
349 s->erxregs[addr >> 2] = val; in sunhme_erx_write()
358 val = s->erxregs[addr >> 2]; in sunhme_erx_read()
379 uint64_t oldval = s->macregs[addr >> 2]; in sunhme_mac_write()
383 s->macregs[addr >> 2] = val; in sunhme_mac_write()
389 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in sunhme_mac_write()
401 val = s->macregs[addr >> 2]; in sunhme_mac_read()
434 s->miiregs[MII_BMSR] |= MII_BMSR_AN_COMP; in sunhme_mii_write()
436 if (!qemu_get_queue(s->nic)->link_down) { in sunhme_mii_write()
437 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_mii_write()
438 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_mii_write()
444 s->miiregs[reg] = data; in sunhme_mii_write()
449 uint16_t data = s->miiregs[reg]; in sunhme_mii_read()
467 /* Mask the read-only bits */ in sunhme_mif_write()
469 val |= s->mifregs[HME_MIFI_CFG >> 2] & in sunhme_mif_write()
506 s->mifregs[addr >> 2] = val; in sunhme_mif_write()
515 val = s->mifregs[addr >> 2]; in sunhme_mif_read()
520 s->mifregs[HME_MIFI_STAT >> 2] = 0; in sunhme_mif_read()
542 qemu_send_packet(qemu_get_queue(s->nic), buf, size); in sunhme_transmit_frame()
547 return (s->etxregs[HME_ETXI_RSIZE >> 2] + 1) << 4; in sunhme_get_tx_ring_count()
552 return s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_OFFSET; in sunhme_get_tx_ring_nr()
557 uint32_t ring = s->etxregs[HME_ETXI_RING >> 2] & ~HME_ETXI_RING_OFFSET; in sunhme_set_tx_ring_nr()
560 s->etxregs[HME_ETXI_RING >> 2] = ring; in sunhme_set_tx_ring_nr()
572 tb = s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_ADDR; in sunhme_transmit()
588 len = HME_FIFO_SIZE - xmit_pos; in sunhme_transmit()
604 if (xmit_pos - len <= csum_offset && xmit_pos > csum_offset) { in sunhme_transmit()
605 sum += net_checksum_add(xmit_pos - csum_offset, in sunhme_transmit()
607 trace_sunhme_tx_xsum_add(csum_offset, xmit_pos - csum_offset); in sunhme_transmit()
609 sum += net_checksum_add(len, xmit_buffer + xmit_pos - len); in sunhme_transmit()
610 trace_sunhme_tx_xsum_add(xmit_pos - len, len); in sunhme_transmit()
623 if (s->macregs[HME_MACI_TXCFG >> 2] & HME_MAC_TXCFG_ENABLE) { in sunhme_transmit()
644 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_transmit()
646 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_transmit()
649 s->etxregs[HME_ETXI_PENDING >> 2] = 0; in sunhme_transmit()
655 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_transmit()
657 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_transmit()
665 return !!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE); in sunhme_can_receive()
672 if (nc->link_down) { in sunhme_link_status_changed()
673 s->miiregs[MII_ANLPAR] &= ~MII_ANLPAR_TXFD; in sunhme_link_status_changed()
674 s->miiregs[MII_BMSR] &= ~MII_BMSR_LINK_ST; in sunhme_link_status_changed()
676 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_link_status_changed()
677 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_link_status_changed()
681 s->mifregs[HME_MIFI_STAT >> 2] = 0xffff; in sunhme_link_status_changed()
687 uint32_t rings = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_RINGSIZE) in sunhme_get_rx_ring_count()
706 return s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_OFFSET; in sunhme_get_rx_ring_nr()
711 uint32_t ring = s->erxregs[HME_ERXI_RING >> 2] & ~HME_ERXI_RING_OFFSET; in sunhme_set_rx_ring_nr()
714 s->erxregs[HME_ERXI_RING >> 2] = ring; in sunhme_set_rx_ring_nr()
730 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE)) { in sunhme_receive()
738 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_PMISC)) { in sunhme_receive()
740 if (((s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff00) >> 8) == buf[0] && in sunhme_receive()
741 (s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff) == buf[1] && in sunhme_receive()
742 ((s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff00) >> 8) == buf[2] && in sunhme_receive()
743 (s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff) == buf[3] && in sunhme_receive()
744 ((s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff00) >> 8) == buf[4] && in sunhme_receive()
745 (s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff) == buf[5]) { in sunhme_receive()
752 } else if (s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_HENABLE) { in sunhme_receive()
755 if (!(s->macregs[(HME_MACI_HASHTAB0 >> 2) - (mcast_idx >> 4)] & in sunhme_receive()
760 return -1; in sunhme_receive()
767 return -1; in sunhme_receive()
775 rb = s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_ADDR; in sunhme_receive()
784 s->sebregs[HME_SEBI_STAT >> 2] |= HME_SEB_STAT_NORXD; in sunhme_receive()
787 return -1; in sunhme_receive()
790 rxoffset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_BYTEOFFSET) >> in sunhme_receive()
808 csum_offset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_CSUMSTART) >> in sunhme_receive()
811 sum += net_checksum_add(len - csum_offset, (uint8_t *)buf + csum_offset); in sunhme_receive()
833 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_receive()
835 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_receive()
856 pci_conf = pci_dev->config; in sunhme_realize()
859 memory_region_init(&s->hme, OBJECT(pci_dev), "sunhme", HME_REG_SIZE); in sunhme_realize()
860 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->hme); in sunhme_realize()
862 memory_region_init_io(&s->sebreg, OBJECT(pci_dev), &sunhme_seb_ops, s, in sunhme_realize()
864 memory_region_add_subregion(&s->hme, 0, &s->sebreg); in sunhme_realize()
866 memory_region_init_io(&s->etxreg, OBJECT(pci_dev), &sunhme_etx_ops, s, in sunhme_realize()
868 memory_region_add_subregion(&s->hme, 0x2000, &s->etxreg); in sunhme_realize()
870 memory_region_init_io(&s->erxreg, OBJECT(pci_dev), &sunhme_erx_ops, s, in sunhme_realize()
872 memory_region_add_subregion(&s->hme, 0x4000, &s->erxreg); in sunhme_realize()
874 memory_region_init_io(&s->macreg, OBJECT(pci_dev), &sunhme_mac_ops, s, in sunhme_realize()
876 memory_region_add_subregion(&s->hme, 0x6000, &s->macreg); in sunhme_realize()
878 memory_region_init_io(&s->mifreg, OBJECT(pci_dev), &sunhme_mif_ops, s, in sunhme_realize()
880 memory_region_add_subregion(&s->hme, 0x7000, &s->mifreg); in sunhme_realize()
882 qemu_macaddr_default_if_unset(&s->conf.macaddr); in sunhme_realize()
883 s->nic = qemu_new_nic(&net_sunhme_info, &s->conf, in sunhme_realize()
884 object_get_typename(OBJECT(d)), d->id, in sunhme_realize()
885 &d->mem_reentrancy_guard, s); in sunhme_realize()
886 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in sunhme_realize()
893 device_add_bootindex_property(obj, &s->conf.bootindex, in sunhme_instance_init()
894 "bootindex", "/ethernet-phy@0", in sunhme_instance_init()
898 static void sunhme_reset(DeviceState *ds) in sunhme_reset() argument
900 SunHMEState *s = SUNHME(ds); in sunhme_reset()
903 s->mifregs[HME_MIFI_CFG >> 2] |= HME_MIF_CFG_MDI0; in sunhme_reset()
906 s->miiregs[MII_ANAR] = MII_ANAR_TXFD; in sunhme_reset()
907 s->miiregs[MII_BMSR] = MII_BMSR_AUTONEG | MII_BMSR_100TX_FD | in sunhme_reset()
910 if (!qemu_get_queue(s->nic)->link_down) { in sunhme_reset()
911 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_reset()
912 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_reset()
916 s->miiregs[MII_PHYID1] = DP83840_PHYID1; in sunhme_reset()
917 s->miiregs[MII_PHYID2] = DP83840_PHYID2; in sunhme_reset()
920 s->mifregs[HME_MIFI_IMASK >> 2] = 0xffff; in sunhme_reset()
921 s->sebregs[HME_SEBI_IMASK >> 2] = 0xff7fffff; in sunhme_reset()
930 VMSTATE_MACADDR(conf.macaddr, SunHMEState),
946 k->realize = sunhme_realize; in sunhme_class_init()
947 k->vendor_id = PCI_VENDOR_ID_SUN; in sunhme_class_init()
948 k->device_id = PCI_DEVICE_ID_SUN_HME; in sunhme_class_init()
949 k->class_id = PCI_CLASS_NETWORK_ETHERNET; in sunhme_class_init()
950 dc->vmsd = &vmstate_hme; in sunhme_class_init()
953 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); in sunhme_class_init()