223     uint32_t rxdmaregs[SUNGEM_MMIO_RXDMA_SIZE >> 2];  member
455     rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];  in sungem_can_receive()
468     kick = s->rxdmaregs[RXDMA_KICK >> 2];  in sungem_can_receive()
469     done = s->rxdmaregs[RXDMA_DONE >> 2];  in sungem_can_receive()
571     rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];  in sungem_receive()
609     kick = s->rxdmaregs[RXDMA_KICK >> 2] & s->rx_mask;  in sungem_receive()
610     done = s->rxdmaregs[RXDMA_DONE >> 2] & s->rx_mask;  in sungem_receive()
625     dbase = s->rxdmaregs[RXDMA_DBHI >> 2];  in sungem_receive()
626     dbase = (dbase << 32) | s->rxdmaregs[RXDMA_DBLOW >> 2];  in sungem_receive()
667     s->rxdmaregs[RXDMA_DONE >> 2] = done;  in sungem_receive()
693     sz = 1 << (((s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_RINGSZ) >> 1) + 5);  in sungem_update_masks()
706     s->rxdmaregs[RXDMA_FSZ >> 2] = 0x140;  in sungem_reset_rx()
707     s->rxdmaregs[RXDMA_DONE >> 2] = 0;  in sungem_reset_rx()
708     s->rxdmaregs[RXDMA_KICK >> 2] = 0;  in sungem_reset_rx()
709     s->rxdmaregs[RXDMA_CFG >> 2] = 0x1000010;  in sungem_reset_rx()
710     s->rxdmaregs[RXDMA_PTHRESH >> 2] = 0xf8;  in sungem_reset_rx()
711     s->rxdmaregs[RXDMA_BLANK >> 2] = 0;  in sungem_reset_rx()
1030     s->rxdmaregs[addr >> 2] = val;  in sungem_mmio_rxdma_write()
1040             (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {  in sungem_mmio_rxdma_write()
1059     val = s->rxdmaregs[addr >> 2];  in sungem_mmio_rxdma_read()
1156             (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {  in sungem_mmio_mac_write()
1444         VMSTATE_UINT32_ARRAY(rxdmaregs, SunGEMState,